{"id":74,"date":"2018-12-07T06:12:20","date_gmt":"2018-12-07T06:12:20","guid":{"rendered":"http:\/\/msp10.epgpbooks.inflibnet.ac.in\/?post_type=chapter&p=74"},"modified":"2018-12-07T06:36:14","modified_gmt":"2018-12-07T06:36:14","slug":"metal-oxide-semiconductor-field-effect-transistor-mosfet","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/chapter\/metal-oxide-semiconductor-field-effect-transistor-mosfet\/","title":{"rendered":"Metal Oxide Semiconductor Field Effect Transistor (MOSFET)"},"content":{"raw":"
\"epgp<\/a>\r\n<\/span><\/div>\r\n \r\n\r\n \r\n\r\n \r\n
    \r\n \t
  1. Introduction<\/strong><\/li>\r\n<\/ol>\r\n \r\n

    MOSFET (Metal Oxide Semiconductor Field Effect Transistor is a unipolar transistor acting as a voltage controlled device where current between the two electrodes \u2018Drain\u2019 and \u2018Source\u2019 is controlled by the applied electric field at another electrode (Gate). Here metal Gate is isolated from the semiconductor by a very thin oxide layer. The characters of metal oxide silicon field effect transistors, or MOSFETs are quite similar to those of JFETs, although there is a difference in their mechanism of production. A replacement of gate-channel p-n junction of JFET is done by a metal oxide silicon capacitors that influences the number of carriers in the channel. The carrier density in the channel is modulated by the applied gate voltage, whereas the width of the channel is hardly affected. Comparison of MOSFTE and JFET is given below:<\/p>\r\n \r\n\r\n\r\n\r\n\r\n\r\n\r\n
    MOSFET<\/strong><\/td>\r\nJFET<\/strong><\/td>\r\n<\/tr>\r\n
    It can be operated in both depletion mode and\r\nenhancement mode<\/td>\r\nIt can be operated only in depletion mode<\/td>\r\n<\/tr>\r\n
    Have high input impedance, thus small input current<\/td>\r\nRelatively low input impedance<\/td>\r\n<\/tr>\r\n
    MOSFETs have higher speed of operation i.e. they\r\nrespond instantaneously with a small change in gate\r\nvoltage<\/td>\r\nJFETs are relatively slower<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n2.\u00a0 Type of MOSFETs<\/strong>\r\n\r\n\"\"\r\n
      \r\n \t
    1. Enhancement mode (E-MOSFET)<\/strong><\/li>\r\n<\/ol>\r\n

      3.1 Schematic of n-channel E-MOSFET<\/strong><\/p>\r\n \r\n

      Figure 1 shows a schematic of a n-channel E-MOSFET. It has \u201cMetal\u201d Gate electrode which is electrically insulated from semiconductor (n-type or p-type) by very thin layer of oxide material usually silicon dioxide. A thin layer of silicon dioxide covers the surface of silicon, which performs three functions: it acts as a protective layer for the silicon surface which ensures stable electrical behavior; it acts as an insulator for the deposition of conductors on its surface, without making electrical contact to the semiconductor; it acts as a dielectric for the capacitor formed by the gate electrode and the substrate. Gate terminal is isolated from current carrying channel, so no current flows into gate.<\/p>\r\n\"\"\r\n

      It consists of a p- Si substrate into which 2 heavily doped n+ region have been diffused namely Source<\/p>\r\n \r\n

      (S) and Drain (D). Metal contact is deposited on oxide layer that covers gap between two n+ diffusion and serves as Gate (G). Here, L is channel length [distance between two n+ region], Z is channel width, d is thickness of oxide layer, NA is acceptor doping concentration in p-type Si, Central section of device corresponds to MOS diode and Source is used as voltage reference.<\/p>\r\n \r\n

      3.2 Detailed operation of n-channel E-MOSFET<\/strong><\/p>\r\n \r\n

      Case I: V<\/strong>G<\/strong> = 0<\/strong><\/p>\r\n \r\n

      Source-to-drain electrodes corresponds to two n+- p junctions connected back to back. Device is off, when VG = 0 as there is no channel between Source and Drain.<\/p>\r\n \r\n\r\nCase II:V<\/strong>G<\/strong> > V<\/strong>T<\/strong> (Inversion condition for MOS)<\/strong>\r\n\r\n \r\n

      Large positive gate voltage [VG > VT] has to be applied to induce a channel below oxide i.e. a surface inversion layer (accumulated electrons) is created. The electron concentration in channel enhances by increasing VG and hence channel conductance can be modulated by VG.<\/p>\r\n\"\"\r\n\r\nFOR V<\/strong>G<\/strong> > V<\/strong>T<\/strong>\r\n\r\n \r\n\r\nCase A: For small value of +V<\/strong>D<\/strong>\r\n\r\n \r\n

      Electron will flow from S to D through conducting channel. Channel acts as a resistance and ID VD (linear region). As long as VD is small, the surface potential will remain almost same throughout channel (i.e. near source and drain regions). The electron concentration will remain same and channel behaves as resistor having<\/p>\r\n\"\"\r\n

      Where, Qn < 0, is the space charge per unit area of inversion layer (or channel) and Z is the channel width.<\/p>\r\n \r\n

      Case B<\/em><\/strong>: For moderate value of +V<\/strong>D<\/strong><\/p>\r\n \r\n

      With increase in V<\/em>D<\/em>, potential will distribute throughout the channel. Potential difference between G and inversion layer will be more near S and very less near D. Thus, electron concentration (Qn) in channel will be relatively less near D, and hence channel resistance increases. I-V curve will bend downward from initial linear variation.<\/p>\r\n \r\n

      Case C: For large V<\/em><\/strong>D<\/em><\/strong> If V<\/em><\/strong>D<\/em><\/strong> further increases (V<\/em><\/strong>Dsat<\/em><\/strong>), the potential drop across oxide near drain will continue to decrease, and may until it falls below the value required to maintain an inversion layer, i.e. width of inversion layer xi at y = L reduced to zero [known as Pinch off point]. At this condition, Drain gets isolated from conducting channel (inversion layer) by a depletion region. The ID will then saturate to a constant value Idsat at VD = VDsat.<\/p>\r\n \r\n

      Case D: As V<\/em><\/strong>D<\/em><\/strong> > V<\/em><\/strong>Dsat<\/em><\/strong>, ID remains as IDsat. The pinch off point P will move towards Source, and effective channel length (L ) will decrease. However, the potential at P will remain at VDsat, and additional voltage in excess of VDsat will drop across depletion region. Thus, number of carriers arriving at point P from Source and hence current flowing from D to S remains the constant.<\/p>\r\n\"\"\r\n\r\n \r\n

      If VG or VGS increases (For Fixed V<\/em>D<\/em>), leads to increases in the inversion layer and thus charge Qn.<\/p>\r\n \r\n

      Therefore, channel resistance decreases or ID increases for a given VD. The pinch off will occur at a higher value of VD.<\/p>\r\n \r\n

      3.3 Study of I-V relationship for n-channel E-MOSFET <\/strong><\/p>\r\n \r\n

      Consider ideal condition and following assumptions<\/p>\r\n\r\n