{"id":142,"date":"2018-12-10T04:32:33","date_gmt":"2018-12-10T04:32:33","guid":{"rendered":"http:\/\/msp10.epgpbooks.inflibnet.ac.in\/?post_type=chapter&p=142"},"modified":"2022-01-07T06:13:04","modified_gmt":"2022-01-07T06:13:04","slug":"charge-transfer-devices-ccd","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/chapter\/charge-transfer-devices-ccd\/","title":{"rendered":"Charge Transfer Devices (CCD)"},"content":{"raw":"
\"epgp<\/a>\r\n<\/span><\/div>\r\n \r\n\r\n \r\n\r\n \r\n
    \r\n \t
  1. Introduction<\/strong><\/li>\r\n<\/ol>\r\n \r\n

    Boyle and Smith invented charge-couple device (CCD) in 1970 and CCD can be contemplated as charge-transfer devices. It is an array of closely spaced MOS devices where information can be stored in the form of charged packets, in the potential wells created in the semiconductor by applying voltages at the gate of an array of MOS devices. CCD can be considered as an integrated version of MOS bucket-brigade device (BBD). It has wide range of applications due to low power consumption and high packing density. CCDs have been classified as: (a) surface-channel CCD (SCCD), buried-channel CCD (BCCD), peristaltic CCD (PCCD) and profiled-peristaltic CCD (PPCCD). Before studying the operation of CCD, it is important to study the transient characteristics of MOS capacitor operating in deep depletion region. The representation of information in CCD is different from that of transistors where instead of charge, current and voltages are used.<\/p>\r\n \r\n

    1.1 MOS capacitor in deep depletion regime<\/strong><\/p>\r\n \r\n

    Consider, a MOS capacitor utilizing p-Si substrate. A positive voltage greater than the threshold voltage is applied on the gate terminal (VG > VT) of MOS. After the application of voltage, the device goes into deep depletion region and the energy band diagram corresponding to MOS capacitor in deep depletion regime is shown in figure 1.<\/p>\r\n\"\"\r\n

    The energy band diagram of MOS capacitor in deep depletion region has already been explained in MOS diode showing the formation of potential well at the semiconductor interface. As evident from figure 1, the formation of inversion layer is not there due to the absence of minority carriers immediately. Thus, the surface potential s0 increases as the large fraction of applied voltage appears across semiconductor. As the time elapsed, electron hole pairs are generated thermally in the deep depletion region. Electrons start diffusing to the Si-SiO2 interface and hence forming an inversion layer. This time interval between the initial creation of deep depletion region and formation of inversion layer is called Thermal relaxation time. Depending on the fabrication process, the thermal relaxation time can vary from seconds to some minutes. Also, thermal relaxation time depends on flat band voltage, gate voltage and density of generation of recombination centers at the Si-SiO2 interface. In CCD, the information in the form of charge has to be transferred well before the thermal relaxation time (i.e. during deep depletion condition) in the potential well. If some injection of information signal charge carriers Qinfo in the semiconductor is done near the oxide interface, there is a formation of deep depletion region (VG > VT) and information signal charge carriers will get accumulated in the potential well and resulting in a decrease in the surface potential to s (as shown in figure 2).<\/p>\r\n \r\n

    \"\"<\/p>\r\n \r\n

    Now in order to examine the variation of surface potential on injection of information signal charge carriers, the relation between the surface potential s and the Qinfo has been derived. The surface potential s and gate voltage VG for non-ideal MOS capacitor are related as:<\/p>\r\n \r\n\r\n\"\"\r\n\r\n\"\"\r\n

    The above equations (4) and (5) depict that for a constant value of gate voltage the surface potential decreases linearly with signal charge.<\/p>\r\n \r\n

    2 .Principle of operation<\/strong><\/p>\r\n \r\n

    The basic structure of charge coupled device is shown in figure 3. This includes a p-Si substrate whose top surface is covered with SiO2 layer. An array of metal electrodes (gates) are deposited on surface of oxide layers (figure 3). These metal electrodes are closely spaced, each of which forms a MOS capacitors. These capacitors can be biased in deep depletion region forming the potential wells, as shown in figure 3. The depth of the potential well is a function of applied voltage at the gate, and becomes more at higher bias. The information signal charge could be transferred from one potential well to other by applying the higher voltage at the respective gate (figure 3).<\/p>\r\n

    \"\"<\/p>\r\n \r\n\r\n2.1 Storage and transfer of charge information<\/strong>\r\n\r\n \r\n

    Consider the following figure 4 which represents a CCD having an array of metal gates. Let, the voltage at one of the electrode is significantly greater (VB > VA, VB > VC) than the voltage at its neighboring electrodes (A and C). If now (t=0) the electrons (charge information) are introduced in the CCD, they will get accumulated in the potential well formed below the electrode B and get confined in the well (figure 4(a)).The information charge could be stored in the well until the time is less than the thermal relaxation time (figure 4(a)).<\/p>\r\n\"\"\r\n\r\n\"\"\r\n\r\n \r\n

    Figure 4(b) is depicting the charge transfer of the process. At time t=t0, the applied potential at the right electrode (C) is increased toVC > VB. The higher potential well results in deeper potential well and\u00a0hence charge (information) could transfer from the potential well under the second electrode, B to the potential well under the electrode, C. Till now, the basic concepts of charge storage and charge transfer have been discussed in a CCD. The charge transfer can be realized practically using a linear array of 3-phase CCD which is explained in the next section.<\/p>\r\n\r\n

      \r\n \t
    1. 3-phase CCD<\/strong><\/li>\r\n<\/ol>\r\n \r\n

      The basic schematic of three-phase CCD is shown in figure 5(a). The electrodes are connected in groups of three and a three phase periodic waveform called clock voltage is used for operation. Figure 5(b) explains the charge transfer process in a 3-phase CCD along a linear array.<\/p>\r\n \r\n\r\n\"\"\r\n

      Figure 5: <\/strong>(a) CCD as a linear array of MOS capacitors where the electrodes are connected in groups of three<\/p>\r\n

      phase periodic waveform (b) the charge (information) transfer process in a 3-phase CCD.<\/p>\r\n \r\n

      The clock voltage waveform for the three phase operation is shown in figure 6 and the time period of the waveform is T. The timing diagram shown in figure 6 is divided into the three waveforms corresponding to three-phases. The waveforms are identical for each phase but shifted sequentially by a time interval of T\/3 with respect to each other as shown in figure 6. The voltage applied at any electrode is either at V1 or at V2 or changing linearly from V1 to V2 during a subinterval of T\/3 (figure 6). When these voltages ( a, b, c) are applied to 3-phase CCD, the charge (information) starts transferring from one potential well to another sequentially as discussed follows.<\/p>\r\n \r\n

      At time t=0,the charges are present under the electrode a1 at voltage \u03d5a with value V2 and there is no charge present under the b electrode as they are at voltage \u03d5b with value V1 for the time interval T\/3. Also, there is no charge present under the C electrode as \u03d5c has completed its fall to V1. During the time interval 0 to T\/3, the voltage \u03d5a decreases to V1,while \u03d5b remains at V2 and the charge gets transferred from the potential well under electrode a1 to the potential well under electrode b1.This transfer process is completed at time t=T\/3. Similarly, at time t=2T\/3 the charge gets transferred to the potential well under the electrode c1.Finally at the full time period of the clock wave T, the charge has been transferred to the potential well under the electrode a2, thus along a linear array the charge has propagated. There is a little loss of charge during the transfer when the time is small as compared to the thermal relaxation time and the information is transferred from the input to the output of the device. For an n-Si- substrate the operation is similar except the voltages V1 and V2 become negative.<\/p>\r\n

      \"\"<\/p>\r\n\r\n

        \r\n \t
      1. Input and output arrangements<\/strong><\/li>\r\n<\/ol>\r\n \r\n

        For use of CCD there is a need of an input to inject the charge and an output to detect the stored charge. The charge carriers at the input can be generated through avalanche injection or optical injection. In avalanche injection, a large voltage pulse is applied to cause an avalanche breakdown in the semiconductor, while in the optical injection electron hole pairs are generated by shining a light on the semiconductor.<\/p>\r\n \r\n

        The commonly used method for minority charge carrier injection is from a p-n junction as in figure 7(a).A n+ type is diffused into the p substrate under an opening in the SiO2 layer. A gating electrode is added for the input gate. The input diode, which acts as a source of electron is connected to the signal to fed electron into the CCD. The voltage at the input gate is low so that no electron enters the channel. During the time interval when the a1 electrode next to the input gate is in high voltage condition, the voltage at the gate is raised to make it on. Now, electrons will start filling the potential well beneath a1 until the energy levels of the electrons in the well become equal to that of source. When the required amount of charge is stored under the electrode a1, the voltage at the input gate is removed so as to isolate the source.<\/p>\r\n\"\"\r\n

        The output arrangement of a CCD consists of a reverse biased p n junction diode as shown in figure 7(b). When the p n junction is reverse biased, the charge carriers are collected. This is same as that of collection of minority carriers by the collector base junction of bipolar transistor. The output voltage can then be observed across a series resistor R.<\/p>\r\n\r\n

          \r\n \t
        1. Fabrication of CCDs<\/strong><\/li>\r\n<\/ol>\r\n

          CCDs are fabricated on silicon wafers and are being processed in a series of complex photolithographic steps involving etching, ion implantation, thin film deposition, metallization, and passivation for defining various functions within the device. The substrate of silicon is electrically doped to form p-type silicon. Various dies are fabricated on each wafer and are tested, and packaged into a ceramic or polymer casing with a glass or quartz window through which light can pass to<\/p>\r\n \r\n\r\n\"\"\r\n

          The effect of traps is eliminated if the channel is moved some distance away from the interface. This condition is achieved in a buried channel CCD (BCCD) as shown in figure 9. An n-type layer is produced on the top of the lightly doped p \u2013Si substrate by ion implantation. Then, the oxidation of wafer is done and n+ diffusion is performed for input and output diodes through the windows etched in oxide. Then, on n+ regions ohmic contacts are made and the layer is covered with series of metal electrodes.<\/p>\r\n

          \"\"<\/p>\r\n

          The operation of BCCD can be understood as: Consider a large positive voltage is applied to the input and the output through n-layer while the gate is held at ground potential. Reverse biasing the substrate of the p-n junction widens the depletion region of the junction on both sides n and p regions. Since, the gate is also biased negative with respect to n-region, below the metal electrodes a field induced depletion region is formed. With increase in the reverse biasing the two depletion regions would meet at distance away from interface, thus potential acquiring maximum value therefore, the charge injected will be attracted in the potential and remain there and this charge can be transferred to other electrode by application of a suitable clock pulse.<\/p>\r\n \r\n

          The difference between the surface and buried CCD is that the electrons forming the charge packet in a SCCD are minority carriers and forms a thin inversion layer near the interface, while in the BCCD the stored charge is of majority carriers that replace some of the electrons removed during depletion region formation.<\/p>\r\n\r\n

            \r\n \t
          1. Summary<\/strong><\/li>\r\n<\/ol>\r\n

            MOS capacitors biased in deep depletion region are the building blocks of charge coupled devices (CCD). One of the most important parameter is thermal relaxation time which is the interval between the initial creation of deep depletion region and formation of inversion layer. The information in the form of charge has to be transferred well before the thermal relaxation time in CCD. The information\u00a0signal charge carriers Qinfo is injected in the semiconductor near the oxide interface and they will get accumulated in the potential well formed at the interface. The operation of CCD can be realised practically using a 3-phase CCD which consists of a linear array of MOS capacitors where the electrodes are connected in groups of three phase periodic waveform. The charge carriers at the input can be generated through avalanche injection or optical injection and can be collected at the output utilising a reverse biased p-n junction diode.<\/p>\r\n\r\n\r\n\r\n\r\n
            you can view video on Charge Transfer Devices (CCD)<\/strong><\/td>\r\n\"\"<\/a><\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>","rendered":"
            \"epgp<\/a>
            \n<\/span><\/div>\n

             <\/p>\n

             <\/p>\n

             <\/p>\n

              \n
            1. Introduction<\/strong><\/li>\n<\/ol>\n

               <\/p>\n

              Boyle and Smith invented charge-couple device (CCD) in 1970 and CCD can be contemplated as charge-transfer devices. It is an array of closely spaced MOS devices where information can be stored in the form of charged packets, in the potential wells created in the semiconductor by applying voltages at the gate of an array of MOS devices. CCD can be considered as an integrated version of MOS bucket-brigade device (BBD). It has wide range of applications due to low power consumption and high packing density. CCDs have been classified as: (a) surface-channel CCD (SCCD), buried-channel CCD (BCCD), peristaltic CCD (PCCD) and profiled-peristaltic CCD (PPCCD). Before studying the operation of CCD, it is important to study the transient characteristics of MOS capacitor operating in deep depletion region. The representation of information in CCD is different from that of transistors where instead of charge, current and voltages are used.<\/p>\n

               <\/p>\n

              1.1 MOS capacitor in deep depletion regime<\/strong><\/p>\n

               <\/p>\n

              Consider, a MOS capacitor utilizing p-Si substrate. A positive voltage greater than the threshold voltage is applied on the gate terminal (VG > VT) of MOS. After the application of voltage, the device goes into deep depletion region and the energy band diagram corresponding to MOS capacitor in deep depletion regime is shown in figure 1.<\/p>\n

              \"\"<\/p>\n

              The energy band diagram of MOS capacitor in deep depletion region has already been explained in MOS diode showing the formation of potential well at the semiconductor interface. As evident from figure 1, the formation of inversion layer is not there due to the absence of minority carriers immediately. Thus, the surface potential s0 increases as the large fraction of applied voltage appears across semiconductor. As the time elapsed, electron hole pairs are generated thermally in the deep depletion region. Electrons start diffusing to the Si-SiO2 interface and hence forming an inversion layer. This time interval between the initial creation of deep depletion region and formation of inversion layer is called Thermal relaxation time. Depending on the fabrication process, the thermal relaxation time can vary from seconds to some minutes. Also, thermal relaxation time depends on flat band voltage, gate voltage and density of generation of recombination centers at the Si-SiO2 interface. In CCD, the information in the form of charge has to be transferred well before the thermal relaxation time (i.e. during deep depletion condition) in the potential well. If some injection of information signal charge carriers Qinfo in the semiconductor is done near the oxide interface, there is a formation of deep depletion region (VG > VT) and information signal charge carriers will get accumulated in the potential well and resulting in a decrease in the surface potential to s (as shown in figure 2).<\/p>\n

               <\/p>\n

              \"\"<\/p>\n

               <\/p>\n

              Now in order to examine the variation of surface potential on injection of information signal charge carriers, the relation between the surface potential s and the Qinfo has been derived. The surface potential s and gate voltage VG for non-ideal MOS capacitor are related as:<\/p>\n

               <\/p>\n

              \"\"<\/p>\n

              \"\"<\/p>\n

              The above equations (4) and (5) depict that for a constant value of gate voltage the surface potential decreases linearly with signal charge.<\/p>\n

               <\/p>\n

              2 .Principle of operation<\/strong><\/p>\n

               <\/p>\n

              The basic structure of charge coupled device is shown in figure 3. This includes a p-Si substrate whose top surface is covered with SiO2 layer. An array of metal electrodes (gates) are deposited on surface of oxide layers (figure 3). These metal electrodes are closely spaced, each of which forms a MOS capacitors. These capacitors can be biased in deep depletion region forming the potential wells, as shown in figure 3. The depth of the potential well is a function of applied voltage at the gate, and becomes more at higher bias. The information signal charge could be transferred from one potential well to other by applying the higher voltage at the respective gate (figure 3).<\/p>\n

              \"\"<\/p>\n

               <\/p>\n

              2.1 Storage and transfer of charge information<\/strong><\/p>\n

               <\/p>\n

              Consider the following figure 4 which represents a CCD having an array of metal gates. Let, the voltage at one of the electrode is significantly greater (VB > VA, VB > VC) than the voltage at its neighboring electrodes (A and C). If now (t=0) the electrons (charge information) are introduced in the CCD, they will get accumulated in the potential well formed below the electrode B and get confined in the well (figure 4(a)).The information charge could be stored in the well until the time is less than the thermal relaxation time (figure 4(a)).<\/p>\n

              \"\"<\/p>\n

              \"\"<\/p>\n

               <\/p>\n

              Figure 4(b) is depicting the charge transfer of the process. At time t=t0, the applied potential at the right electrode (C) is increased toVC > VB. The higher potential well results in deeper potential well and\u00a0hence charge (information) could transfer from the potential well under the second electrode, B to the potential well under the electrode, C. Till now, the basic concepts of charge storage and charge transfer have been discussed in a CCD. The charge transfer can be realized practically using a linear array of 3-phase CCD which is explained in the next section.<\/p>\n

                \n
              1. 3-phase CCD<\/strong><\/li>\n<\/ol>\n

                 <\/p>\n

                The basic schematic of three-phase CCD is shown in figure 5(a). The electrodes are connected in groups of three and a three phase periodic waveform called clock voltage is used for operation. Figure 5(b) explains the charge transfer process in a 3-phase CCD along a linear array.<\/p>\n

                 <\/p>\n

                \"\"<\/p>\n

                Figure 5: <\/strong>(a) CCD as a linear array of MOS capacitors where the electrodes are connected in groups of three<\/p>\n

                phase periodic waveform (b) the charge (information) transfer process in a 3-phase CCD.<\/p>\n

                 <\/p>\n

                The clock voltage waveform for the three phase operation is shown in figure 6 and the time period of the waveform is T. The timing diagram shown in figure 6 is divided into the three waveforms corresponding to three-phases. The waveforms are identical for each phase but shifted sequentially by a time interval of T\/3 with respect to each other as shown in figure 6. The voltage applied at any electrode is either at V1 or at V2 or changing linearly from V1 to V2 during a subinterval of T\/3 (figure 6). When these voltages ( a, b, c) are applied to 3-phase CCD, the charge (information) starts transferring from one potential well to another sequentially as discussed follows.<\/p>\n

                 <\/p>\n

                At time t=0,the charges are present under the electrode a1 at voltage \u03d5a with value V2 and there is no charge present under the b electrode as they are at voltage \u03d5b with value V1 for the time interval T\/3. Also, there is no charge present under the C electrode as \u03d5c has completed its fall to V1. During the time interval 0 to T\/3, the voltage \u03d5a decreases to V1,while \u03d5b remains at V2 and the charge gets transferred from the potential well under electrode a1 to the potential well under electrode b1.This transfer process is completed at time t=T\/3. Similarly, at time t=2T\/3 the charge gets transferred to the potential well under the electrode c1.Finally at the full time period of the clock wave T, the charge has been transferred to the potential well under the electrode a2, thus along a linear array the charge has propagated. There is a little loss of charge during the transfer when the time is small as compared to the thermal relaxation time and the information is transferred from the input to the output of the device. For an n-Si- substrate the operation is similar except the voltages V1 and V2 become negative.<\/p>\n

                \"\"<\/p>\n

                  \n
                1. Input and output arrangements<\/strong><\/li>\n<\/ol>\n

                   <\/p>\n

                  For use of CCD there is a need of an input to inject the charge and an output to detect the stored charge. The charge carriers at the input can be generated through avalanche injection or optical injection. In avalanche injection, a large voltage pulse is applied to cause an avalanche breakdown in the semiconductor, while in the optical injection electron hole pairs are generated by shining a light on the semiconductor.<\/p>\n

                   <\/p>\n

                  The commonly used method for minority charge carrier injection is from a p-n junction as in figure 7(a).A n+ type is diffused into the p substrate under an opening in the SiO2 layer. A gating electrode is added for the input gate. The input diode, which acts as a source of electron is connected to the signal to fed electron into the CCD. The voltage at the input gate is low so that no electron enters the channel. During the time interval when the a1 electrode next to the input gate is in high voltage condition, the voltage at the gate is raised to make it on. Now, electrons will start filling the potential well beneath a1 until the energy levels of the electrons in the well become equal to that of source. When the required amount of charge is stored under the electrode a1, the voltage at the input gate is removed so as to isolate the source.<\/p>\n

                  \"\"<\/p>\n

                  The output arrangement of a CCD consists of a reverse biased p n junction diode as shown in figure 7(b). When the p n junction is reverse biased, the charge carriers are collected. This is same as that of collection of minority carriers by the collector base junction of bipolar transistor. The output voltage can then be observed across a series resistor R.<\/p>\n

                    \n
                  1. Fabrication of CCDs<\/strong><\/li>\n<\/ol>\n

                    CCDs are fabricated on silicon wafers and are being processed in a series of complex photolithographic steps involving etching, ion implantation, thin film deposition, metallization, and passivation for defining various functions within the device. The substrate of silicon is electrically doped to form p-type silicon. Various dies are fabricated on each wafer and are tested, and packaged into a ceramic or polymer casing with a glass or quartz window through which light can pass to<\/p>\n

                     <\/p>\n

                    \"\"<\/p>\n

                    The effect of traps is eliminated if the channel is moved some distance away from the interface. This condition is achieved in a buried channel CCD (BCCD) as shown in figure 9. An n-type layer is produced on the top of the lightly doped p \u2013Si substrate by ion implantation. Then, the oxidation of wafer is done and n+ diffusion is performed for input and output diodes through the windows etched in oxide. Then, on n+ regions ohmic contacts are made and the layer is covered with series of metal electrodes.<\/p>\n

                    \"\"<\/p>\n

                    The operation of BCCD can be understood as: Consider a large positive voltage is applied to the input and the output through n-layer while the gate is held at ground potential. Reverse biasing the substrate of the p-n junction widens the depletion region of the junction on both sides n and p regions. Since, the gate is also biased negative with respect to n-region, below the metal electrodes a field induced depletion region is formed. With increase in the reverse biasing the two depletion regions would meet at distance away from interface, thus potential acquiring maximum value therefore, the charge injected will be attracted in the potential and remain there and this charge can be transferred to other electrode by application of a suitable clock pulse.<\/p>\n

                     <\/p>\n

                    The difference between the surface and buried CCD is that the electrons forming the charge packet in a SCCD are minority carriers and forms a thin inversion layer near the interface, while in the BCCD the stored charge is of majority carriers that replace some of the electrons removed during depletion region formation.<\/p>\n

                      \n
                    1. Summary<\/strong><\/li>\n<\/ol>\n

                      MOS capacitors biased in deep depletion region are the building blocks of charge coupled devices (CCD). One of the most important parameter is thermal relaxation time which is the interval between the initial creation of deep depletion region and formation of inversion layer. The information in the form of charge has to be transferred well before the thermal relaxation time in CCD. The information\u00a0signal charge carriers Qinfo is injected in the semiconductor near the oxide interface and they will get accumulated in the potential well formed at the interface. The operation of CCD can be realised practically using a 3-phase CCD which consists of a linear array of MOS capacitors where the electrodes are connected in groups of three phase periodic waveform. The charge carriers at the input can be generated through avalanche injection or optical injection and can be collected at the output utilising a reverse biased p-n junction diode.<\/p>\n\n\n\n
                      you can view video on Charge Transfer Devices (CCD)<\/strong><\/td>\n\"\"<\/a><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"author":3,"menu_order":7,"template":"","meta":{"pb_show_title":"on","pb_short_title":"","pb_subtitle":"","pb_authors":["dr-ayushi-paliwal","dr-monika-tomar"],"pb_section_license":""},"chapter-type":[],"contributor":[59,58],"license":[],"class_list":["post-142","chapter","type-chapter","status-publish","hentry","contributor-dr-ayushi-paliwal","contributor-dr-monika-tomar"],"part":3,"_links":{"self":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/chapters\/142","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/chapters"}],"about":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/wp\/v2\/types\/chapter"}],"author":[{"embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/wp\/v2\/users\/3"}],"version-history":[{"count":9,"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/chapters\/142\/revisions"}],"predecessor-version":[{"id":606,"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/chapters\/142\/revisions\/606"}],"part":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/parts\/3"}],"metadata":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/chapters\/142\/metadata\/"}],"wp:attachment":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/wp\/v2\/media?parent=142"}],"wp:term":[{"taxonomy":"chapter-type","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/pressbooks\/v2\/chapter-type?post=142"},{"taxonomy":"contributor","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/wp\/v2\/contributor?post=142"},{"taxonomy":"license","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/msp10\/wp-json\/wp\/v2\/license?post=142"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}