9 Volatile and Non Volatile Memories

Dr. Ayushi Paliwal and Dr. Monika Tomar

  1. Introduction

 

Memory arrays often account for the majority of transistors in a CMOS system-on-chip. Random access memory (RAM) can be accessed with a specific address and has a latency independent of the address. Whereas, serial access memories have sequential accessing and thus requires no address. Another type of memory array is Content addressable memory can be determined by address(es) which contain data that matches a specified key. Now, Random access memory can be further classified as read-only memory (ROM) or read/write memory (RAM). Another important classification is volatile and nonvolatile memory. Memory is retained in Volatile memories as long as power is applied, while data is retained indefinitely in nonvolatile memory. RAM is generally used in respect to volatile memory, while ROM is synonymously used with nonvolatile memory.

 

 

Volatile RAM is further divided into static structures and dynamic structures. Static cells utilize some form of feedback in order to maintain their present state, however, dynamic cells make use of charge which gets stored on a floating capacitor through the access transistor. Static RAMs (SRAMs) responds faster and less bothersome, but they need more area per bit as compared to their dynamic counterparts (DRAMs). Nonvolatile memories are categorized into five types of memory. Mask ROM whose contents are hardwired during fabrication which cannot be changed. Another one is programmable ROM (PROM) which can be programmed once after fabrication by blowing on-chip fuses with a special high programming voltage. Next is an erasable programmable ROM (EPROM) which can be programmed by storing charge on a floating gate. It can be erased by exposure to ultraviolet (UV) light for several minutes to knock the charge off the gate. The electrically erasable programmable ROMs (EEPROMs) are similar to ROMs, but the data can only be erased in microseconds with the help of on-chip circuitry. Flash memories erases the entire block of data as compared to individual bits and thus are variant of EEPROM. These flash memories are successfully replacing the other commercially available non-volatile memories used in CMOS systems due to their good density and ease in integration with system reprogrammability,

 

Memory cells can have one or more ports for access. For both read/write memory, every port can be used as read-only, write-only, or both read and write operation. Consider a memory array containing 2n words of 2m bits each where each bit is getting stored in a memory cell. Figure 2 demonstrates the architecture of a small memory array containing 16 4-bit words (for example n = 4, m = 2). Figure 2(a) indicates the most basic design of a memory array which uses one row per word and one column per bit. By asserting the wordline, row decoder activates one of the rows using the address. During a read operation, the cells on this wordline drive the bitlines, which may have been conditioned to a known value in advance of the memory access. To detect the data column circuitry is utilized by employing amplifiers or buffers. A typical memory array may have thousands or millions of words of only 8–64 bits each, which would be difficult to fit in the chip floorplan, therefore, the array is often folded into fewer rows of more columns. After folding, each row of the memory contains 2k words, so the array is physically organized as 2n–k rows of 2m+k columns or bits. Figure 2(b) shows a two-way fold (k = 1) with eight rows and eight columns. The column decoder controls a multiplexer in the column circuitry to select 2m bits from the row as the data to access. Larger memories are generally built from multiple smaller subarrays so that the wordlines and bitlines remain reasonably short, fast, and low in power dissipation. SRAM is the most widely used form of on-chip memory which also illustrates all the issues of cell design, decoding, and column circuitry design.

2. SRAM

 

Static RAMs use a memory cell with internal feedback that retains its value as long as power is applied and has the following advantages:

 

Denser than flip-flops

 

Compatible with standard CMOS processes.Faster and easier to use than DRAM.For these reasons, SRAMs are widely used in applications from caches to register files to tables to scratchpad buffers. The SRAM consists of an array of memory cells along with the row and column circuitry.

 

a. SRAM Cells

 

A SRAM cell needs to be able to read and write data and to hold the data as long as the power is applied. An ordinary flip-flop could accomplish this requirement, but the size is quite large. A typical 6T SRAM cell is shown in figure 3 that can be an order of magnitude smaller than a flip-flop.

 

The 6T cell achieves its compactness at the expense of more complex peripheral circuitry for reading and writing the cells. It contains a pair of weak cross-coupled inverters holding the state and a pair of access transistors to read or write the state. The cell is written by driving the desired value and its complement onto the bitlines, bit and bit_b, then raising the wordline, word. It is read by precharging the two bitlines high, then allowing them to float. When word is raised, bit or bit_b pulls down, indicating the data value.

  1. DRAM

 

Dynamic RAMs (DRAMs) uses capacitor to store their contents as charge rather than in a feedback loop. Hence, the basic cell of DRAM is substantially smaller than SRAM and it requires to be periodically read and refreshed so that its contents do not leak away. Commercial DRAMs are built in specialized processes optimized for dense capacitor structures. They offer a factor of 10–20 greater density (bits/cm2) than high-performance SRAM built in a standard logic process, but they also have much higher latency. Figure 4 shows a 1-transistor (1T) dynamic RAM cell consists of a transistor and a capacitor where the cell is accessed by asserting the wordline to connect the capacitor to the bitline. On a read, the bitline is first precharged to VDD/2. When the wordline rises, the capacitor shares its charge with the bitline, causing a voltage change V that can be sensed, as shown in Figure 4 (b).

 

The cell contents at x are disturbed by read, so the cell must be rewritten after each read. The bitline is driven high or low on a write operation, and the voltage is constrained onto the capacitor. A few DRAMs drive the wordline to VDDP = VDD + Vt to stay away from a corrupted level when writing a ‘1.’ To achieve a good density, DRAM capacitor Ccell must be as physically small. However, the bitline is contacted to many DRAM cells and has a relatively large capacitance Cbit. Thus, the bitline capacitance is typically larger than the cell capacitance. According to the charge-sharing equation, the voltage swing on the bitline during readout is

 

  1. Read Only Memory (ROM)

 

Read-Only Memory (ROM) cells can be built with only one transistor per bit of storage. A ROM is a nonvolatile memory structure in that the state is retained indefinitely—even without power. A ROM array is commonly implemented as a single-ended NOR array. Commercial ROMs are normally dynamic, although pseudo-nMOS is simple and suffices for small structures. As in SRAM cells and other footless dynamic gates, the wordline input must be low during precharge on dynamic NOR gates. In situations where DC power dissipation is acceptable and the speed is sufficient, the pseudo-nMOS ROM is the easiest to design, requiring no timing. The DC power dissipation can be significantly reduced in multiplexed ROMs by placing the pullup transistors after the column multiplexer. Figure 5 (a) shows a 4-word by 6-bit ROM using pseudo-nMOS pullups with the following contents:

 

word0: 01010, word1: 011001, word2: 100101, word3: 101010.

 

The contents of the ROM can be symbolically represented with a dot diagram in which dots indicate the presence of 1s, as shown in Figure 5(b). The dots correspond to nMOS pulldown transistors connected to the bitlines, but the outputs are inverted.

  1. Serial Access Memories

 

Utilizing the fundamental SRAM cell as well as registers, we can build a variety of serial access memories including shift registers and queues. These memories avoid the need for external logic to track addresses for reading or writing.

  1. Shift Registers

A shift register is ordinarily utilized in signal-processing applications to store and delay information. Figure 6(a) demonstrates a basic 4-stage 8-bit shift register constructed from 32 flip-flops. As there is no logic between the registers, specific care must be taken that hold times are fulfilled. The RAM is arranged as a circular support with a couple of counters indicating where the information is read and written. The read counter is set to the first entry and the write counter to the last entry on reset, as demonstrated in figure 6(b). On the other hand, the counters in an N-stage shift register can utilize two 1-of-N hot registers to track which entries should be read and written. Again, one is initialized to point to the first entry and the other to the last entry. These registers can drive the specifically without the requirement for a different decoder, as appeared in Figure 6(c). The tapped delay line is a shift register variant that offers a variable number of stages of delay.

 

  1. Queues (FIFO, LIFO)

 

Queues allow data to be read and written at variable speeds. Figure 7 demonstrates an interface to a queue. The read and write operations each are monitored by their own clocks that may be asynchronous. The queue asserts the FULL flag when there is no room remaining in which we can write data and an EMPTY flag is there when there is no data to read. Due to other framework delays, a few lines additionally give ALMOST-FULL and ALMOST-EMPTY banners to impart the looming state and end write or read requests. The queue inside keeps up read and write pointers demonstrating which information ought to be gotten to next. As with a shift register, the pointers can be counters or 1-of-N hot registers.

 

First In First Out (FIFO) queues are generally employed to buffer data between two asynchronous streams. Like a shift register, the FIFO is sorted out as a round support. The FIFO becomes empty on reset, and both the pointes i.e., read and write are set to the first element. On a write, the write pointer advances to the next element. If it is related to catch the read pointer, the FIFO is FULL. On a read operation, the pointer of read advances to the next subsequent element. The FIFO becomes empty again, on catching the write pointer. Last In First Out (LIFO) queues, also known as stacks, are utilized as a part of utilizations, for example, subroutine or intrude on stacks in microcontrollers. The LIFO utilizes a solitary pointer for both read and write. On reset, the pointer is instated to the principal component and the LIFO is EMPTY. On a write, the pointer is increased. In the event that it achieves the last component, the LIFO is FULL.

  1. Content-Addressable Memory

The CAM acts as an usual SRAM that can be read or written given adr and data, yet additionally performs coordinating operations. Matching asserts a matchline output for each word of the CAM that usually contains a predetermined key. A typical utilization of CAMs is translation lookaside buffers (TLBs) in microprocessors supporting virtual memory. The virtual address is given as the key to the TLB CAM. On the off chance that this address is in the CAM, the relating matchline is stated. This matchline can fill in as the wordline to get to a RAM containing the related physical address. Figure 8 demonstrates a total 4 × 4 CAM array. It comprises of an array of cells, a decoder, and column circuitry. However, each row also produces a dynamic matchline. The matchlines are precharged with the clocked pMOS transistors. The miss signal is produced with a distributed pseudo-nMOS NOR. At the point when the matchlines are utilized to get to a RAM, the monotonicity issue must be considered. At first, all the matchlines are high. During CAM operation, the lines pull down, leaving at most one line affirmed to demonstrate which push contains the key. Be that as it may, the RAM requires a monotonically rising

  1. Programmable Logic Arrays

 

A programmable logic array (PLA) exhibiting a normal structure to execute combinational logic determined in sum-of-products canonical form. Some finite state machines are formed by PLA’s only if the outputs are fed back to inputs through registers. PLAs were most prevalent in the beginning of VLSI when two-level logic minimization was surely known, however multilevel logic optimizers were as yet juvenile. They are thick and quick approaches to execute basic capacities, and with reasonable CAD support, are anything but difficult to change when logic bugs are found. Logic synthesis devices have significantly enhanced and now control logic is generally used. Also, pseudo-nMOS PLAs disperse static power, while dynamic PLAs require cautious plan of timing chains.

  1. Summary

 

Various types of memories SRAM and DRAMs Read Only memory (ROM) Serial Access memories: Shift register, QueuesContent Addressable Memory, Programmable Logic arrays

 

References:

 

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