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Dr. Ayushi Paliwal and Dr. Monika Tomar

1.Introduction

A semiconductor is generally defined as a material with electrical conductivity or resistivity lying between that of a metal and an insulator. The best known semiconductor is silicon (Si) with a band gap of around 1.1 eV. Semiconductors can be elemental or compounds. Elemental semiconductors, such as silicon (Si) and Germanium (Ge) consist of single type of atoms and have similar tetrahedrally bonded crystal structures. Compound semiconductors are formed from elements of group III and V or II and VI of periodic table. Pure semiconductors are usually single crystals of pure silicon or germanium. They are insulators at very low temperature. Upon increasing the temperature, some of the electrons gain thermal energy and are free to move and conduct electricity. These electrons leave behind vacancies or holes which carry a positive charge equal in magnitude to charge of an electron. These holes can also act as current carriers. So, a semiconductor consists of two types of charge carriers- electrons and holes. Semiconductors can be doped by pentavalent or trivalent elements to increase the concentration of electrons and holes. These elements can act as electron donors or acceptors. Silicon, being a tetravalent atom, contains four electrons in its outer most shell. A pentavalent atom (such as phosphorous, arsenic, antimony) will replace a silicon atom and donate one extra electron. A trivalent atom (such as aluminum, boron, gallium) will act as electron acceptor giving rise an extra hole. Semiconductors having electrons as the majority charge carriers are known as n-type semiconductors whereas those having holes as the majority carriers are known as p-type semiconductors.

pn junction diode is the fundamental unit of all electronic circuits and devices. It is a two element device with both p-type and n-type semiconductors. The term ‘diode’ was originally coined to refer to vacuum tubes that had two electrodes, an anode and a cathode. They could be contrasted with triodes, tetrodes, pentodes, etc., which were vacuum tubes with three, four or five electrodes. Originally diodes were simply rectifiers. Electrons would flow in a vacuum diode from a heated cathode through the vacuum to the anode when the anode was made positive with respect to the cathode, but when the applied voltage was reversed, no current would flow because the anode was not a source of electrons. So, the device would only conduct electricity when the anode was the more positive electrode. Later, when semiconductor devices were produced that exhibited similar rectifying properties, they were called diodes too, though the terms anode and cathode are less often used.

2.Semiconductor Growth techniques:

2.1 Crystal growth techniques

Semiconductors can be in bulk as well as thin film form. The basic techniques for growth of semiconductor single crystals are as follows:

1. Czochralski Method

This method utilizes a seed crystal of the material to be grown. A crucible containing the raw material in polycrystalline form is heated so as to melt the material. The seed crystal is lowered into the crucible and withdrawn with continuous rotation. The material solidifies into the same orientation as that of the seed crystal. This technique uses an apparatus called a crystal puller whose schematic is shown in figure 1.

The puller has three main components:

(a) a furnace with power supply which includes a crucible made of fused-silicon( 2), arrangement for rotation (clockwise), a graphite suspector, a rotation mechanism (clockwise) and a heating element.

(b) An arrangement for pulling crystal including a seed holder and rotation mechanism (counter clockwise);

(c) an ambient control which includes a gas source (such as argon), a flow control and exhaust system.

The puller microcontrolled control system for controlling various process parameter such as temperature, crystal diameter, pull rate and rotation speeds. In crystal growing process let us say of silicon, polycrystalline silicon (EGS) is placed in the crucible and the furnace is heated above the melting temperature of silicon. For large diameters silicon ingots an external field is applied to the basic Czochralski puller. The purpose of external magnetic field is to control the concentration of defects, impurities and oxygen contents. The boron trioxide cap is essential for capping the silicon melt and also in GaAs melt it prevents the arsenic loss when the pressure on the surface is above atmospheric pressure.

In order to produce doped semiconductors, the dopant can be introduced into the melt along with the raw material. However, the limitation of the method is that the crucible material (usually graphite) and ambient gas can lead to incorporation of impurities.

1. Float zone process

In order to grow semiconductor crystals with lower contaminations, the float zone process is preferred over Czochialski technique. The seed crystal placed on a high purity polycrystalline rod at the bottom is held in a vertical position and rotated. This whole arrangement is enclosed in quartz envelope having maintained inert atmosphere (argon). Now, a small zone of the crystal is melted using a radio-frequency heater, which traverses the length of the rod while moving upward from the seed. The molten silicon is retained by surface tension between the melting and growing silicon faces. As the floating zone move upwards, a single crystal silicon freezes at the zone’s retreating end and grows as an extension of the seed crystal. Float zone process generally produces materials having higher resistivities as compared to Czochralski process because it can be used to purify the crystal more easily.

Bridgman Method

This method is similar to Czochralski method except that in this case the temperature in the vicinity of the seed crystal is kept below its melting point. The seed crystal is also placed in the crucible along with the polycrystalline material. However, a temperature gradient is maintained across the furnace in which crucible is placed. The schematic of the process is shown in figure 3.

After a crystal is grown, it is separated from the seed and the ingot left is shaped and sliced into wafers.This wafer can then be used as the preliminary material for fabrication of semiconductors devices and ICs.

2.2 Thin film growth techniques

Apart from bulk single crystals, semiconductors can also be grown in the form of thin films over a substrate. They provide higher surface to volume ratio and are extensively used in device and IC fabrication. There are numerous techniques to produce semiconductor thin films. However, to ensure good quality films with minimum strain, the structure of the film and the substrate should be similar, which is also known as epitaxial growth. The single crystalline substrate in this case, acts as the seed. When the same material is deposited over the substrate, it is known as homoepitaxy whereas when a different material (but of similar structure) is deposited, it is known as heteroepitaxy. There are various techniques for epitaxial growth of semiconductor thin films depending on the phase of the material to be grown (solid, liquid, gas) as follows:

2.2.1  Chemical Vapor Deposition (CVD)

Various gases containing the material to be deposited are introduced into a reactor. Upon reacting, the material is deposited in the form of a thin film on a substrate placed inside the reactor. In a typical CVD system, the reactant gases, known as precursor gases, are inserted into the chamber. Upon passing through this chamber, they encounter the substrate which is placed at some temperature where they react and form solid films shown in figure 4.

The gas flow and the temperature of the substrate are the two parameters that should be controlled in order to produce good quality films.CVD has number of advantages such as flexibility of wide range of precursors, uniform thickness, conformality etc. Moreover, it does not require ultra high vacuum. But it has certain drawbacks in terms of safety and health hazards of the precursors.

2.2.2  Molecular Beam Epitaxy (MBE)

The source material and the substrate are kept in anultra high vacuum chamber. The source material is heated and the vapors are taken out of a cavity such that they take the form of a molecular beam. This collimated beam is then aimed at the substrate which is kept at some temperature. In this process, source material is placed in a crucible which is heated to an optimum temperature. Thus evaporating the material and resulting in thermal energy molecular beams. The growth conditions can be controlled more precisely as compared to other techniques as a consequence of control over beam flux. Moreover, due to the presence of ultra high vacuum, various in situ analytical processes can be carried out to check and control of the process. MBE is carried out in conditions far away from thermal equilibrium since it is a vacuum based process. Schematic of MBE setup is shown in figure 5.

2.2.3 Liquid Phase Epitaxy (LPE)

Cooling of a solution containing the material to be deposited leads to the precipitation of the solute on the substrate. The system is cooled below the saturation temperature. It is similar to seeded growth bulk crystal growth techniques but takes place at relatively lower temperatures. However, unlike MBE, it occurs under equilibrium conditions. It is a comparatively safer and cheaper technique.

In addition to this, there are certain physical vapor deposition techniques to grow thin films.

1. Thermal Evaporation:

The material to be deposited (target) is heated and evaporated by resistive heating method under vacuum resulting in a thin film at the substrate.

2. Electron Beam Evaporation:

If the heating of the target material is carried out by focused electron beams, the process is known as electron beam evaporation.

3. Sputtering:

The target material to be deposited is bombarded by high energy ions of inert gas such as Argon which can be generated using RF or DC source. The target atoms are ejected out due to momentum transfer and finally settled at the substrate resulting in the formation of a thin film.

3.p-n JUNCTION

3.1 Different growth techniques to fabricate a pn junction

There are various techniques to fabricate a pn junction and they are explained in detail as follows-

3.1.1 Grown junction:

It is similar to the Czochralski method where a seed crystal melt is used to produce single crystal. However, in this method, one kind of dopant (either n type or p type) is introduced into the melt during the crystal growth. After some time, the other dopant is added into the melt with a concentration higher than the concentration of the initial impurity. This abrupt change in the impurity results in the formation of a pn junction. So, a single crystal consists of p and n type semiconductors.

3.1.2 Alloyed junction:

An alloy is created between a doped semiconductor and a metal containing other type of dopant. For e.g. a small piece of metal containing the p-type impurity is placed on a n-type semiconductor and heated at a high temperature in inert atmosphere such that the metal melts and a part of n and p type impurities are alloyed. The molten portion is then cooled and solidified forming a pn junction.

3.1.3 Diffused junction:

The p-type/n-type semiconductor is heated at a high temperature in the presence of gases containing n-type/p-type impurities. The dopant atoms diffuse into the bulk crystal as a result of the concentration gradient. Some of the host atoms leave their lattice sites at high temperatures and create vacancies which may be occupied by the dopant atoms. SiO2 layer is used as a mask to protect different regions of the semiconductor so that various geometries can be created. Diffusion is carried out under two steps. In the first step, known as the pre deposition step, the impurities are introduced upto a certain depth (around one tenth of a micron). Once these impurities have been introduced, they are embedded deeper into the semiconductor, without more impurities being added. This is done by removing the source of dopants and passing oxygen gas at high temperatures leading to the formation of oxide layer on the surface which seals the impurities. This second step is known as drive in diffusion. This is the most common method used in IC fabrication.

3.1.4  Ion implanted junction:

The dopant ions are accelerated at very high speed and bombarded on the surface of the semiconductor. These ions replace the semiconductor atoms upon collision upto a certain depth where a pn junction is created. Before the bombardment of ions, SiO2 layer is deposited on the top of the semiconductor and certain regions are etched. The ion energies are typically in the range 30-300 keV. When the ion displaces the atom from its lattice site, the material becomes amorphous in that region and can be crystallized by annealing i.e. heating at a certain temperature. The concentration of impurities can be controlled precisely in this case.

When p and n-type semiconductors are brought in contact, holes diffuse from p side to n side due to lesser concentration of holes in the n type semiconductor. Similarly, the electrons from the n type semiconductor diffuse from the n-side to the p-side. This movement of electrons and holes leads to the flow of diffusion current across the junction. These holes and electrons leave behind negatively charged acceptor ions and positively charged donor ions in the p and n regions respectively. As a result, a negative charge region is created on p side and a positive charge region is created on the n side near the junction. The space charge region created on both sides of the junction resist further movement of the charge carriers because of the potential barrier. Electrons crossing from n side to p side are repelled by the negative charge whereas holes crossing from p side to n side are repelled by the positive charge. Also, an electric field is created resulting in a drift current. In equilibrium, the currents balance each other and net current across the junction is zero. Now, when a forward bias is applied to the pn junction, the depletion layer width decreases and current flows across the junction. On application of reverse bias, the depletion layer width increases and only small reverse current flows.

3.2 Energy band diagram of pn junction and formation of depletion region

As evident from figure 6, when a pn junction is formed the condition of alignment of fermi level leads to band bending and the valence and conduction bands in an n-type material are at slightly lower energy levels than the valence and conduction bands in a p-type material. This may also be due to difference in the atomic characteristics of the pentavalent and trivalent impurity atoms. There will be a possibility of the diffusion of the free electrons in the n region occupying the upper part of the conduction band across the junction (they do not require any additional energy) and temporarily become free electrons in the lower part of the p-region conduction band.

As the diffusion of the electrons continues, the depletion region is formed consisting of immobile charge carriers due to the recombination of electrons from n-side and holes from p-side. An energy diagram for a pn junction at the instant of depletion region formation is shown in figure 6. Soon, there are no electrons left in the n-region conduction band with enough energy to move across the junction to the p-region conduction band, as indicated by the alignment of the top of the n-region conduction band and the bottom of the p-region conduction band as shown in figure 6. At this point, the junction is at equilibrium; and the formation of depletion region is complete because diffusion has ceased. There is an energy gradient across the depletion region which acts as an “energy hill” denoted by V0 in figure 6 which can electron must have in order to climb to get to the p region.

3.3 Forward and reverse biasing of pn junction diode

3.3.1 Forward Bias

To bias the diode, we apply a dc voltage across it and forward bias is the condition that allows current through the pn junction. Figure 7(a) shows a that a positive terminal of the dc bias voltage source is connected to p-side and negative terminal to the n-side in the direction in forward bias configuration. This external bias voltage is designated as Vf which is required for conduction in forward bias. A second requirement is that the bias voltage, Vf, must be greater than the barrier potential. When a diode is forward biased, the negative side of the bias-voltage source pushes the free electrons (majority carriers) from n-side towards the pn junction. This leads to the flow of free electrons called as forward current. The applied bias-voltage source must provide sufficient energy to the free electrons so that they can overcome the barrier potential of the depletion region and move on through into the p region. On reaching the p-region, these conduction electrons have lost enough energy to immediately combine with the holes in the valence band.

Now the electrons are in the valence band in the p region and they have lost lot of energy in overcoming the barrier potential to remain in the conduction band. Since unlike charges attract, the positive side of the bias-voltage source attracts the valence electrons towards the left end of the p region. The holes in the p region provide the medium for these valence electrons to move through the p region and they move towards the left from one hole to the next. As the electrons flow out of the p region through the external connection (conductor) and to the positive side of the bias-voltage source, they leave holes behind in the p region; at the same time, these electrons become conduction electrons in the metal conductor. Recall that the conduction band in a conductor overlaps the valence band so that it takes much less energy for an electron to be a free electron in a conductor than in a semiconductor. So, there is a continuous availability of holes effectively moving toward the pn junction to combine with the continuous stream of electrons as they come across the junction into the p region.

Effect of forward bias on the depletion region: With more electrons flowing into the depletion region, the number of positive ions is reduced same as that of reduction in number of negative ions with more holes effectively flow into the depletion region on the other side of the pn junction. This reduction in positive and negative ions leads to depletion region to narrow during forward bias as indicated in figure 7 (a).

The electric field between the positive and negative ions in the depletion region on either side of the junction creates an “energy hill” and cross the depletion region. The energy that the electrons require in order to pass through the depletion region is equal to the barrier potential. In other words, the electrons give up an amount of energy equivalent to the barrier potential when they cross the depletion region. This energy loss results in a voltage drop across the pn junction equal to the barrier potential. An additional small voltage drop occurs across the p and n regions due to the internal resistance of the material. For doped semiconductive material, this resistance, called the dynamic resistance, is very small and can usually be neglected.

3.3.2 Reverse Bias

Reverse bias is the condition that essentially prevents current through the diode. Figure 7(b) shows a positive side of battery is connected to the n region of the diode and the negative side to the p region dc voltage source connected across a diode in the direction to produce reverse bias. This external bias voltage is designated as Vr. Here, the depletion region is shown much wider than in forward bias or equilibrium. The positive side of the bias-voltage source “pulls” the free electrons, which are the majority carriers in the n region, away from the pn junction. As the electrons flow towards the positive side of the voltage source, additional positive ions are created. This results in a widening of the depletion region and depletion of majority carriers.

The initial flow of charge carriers is transitional and lasts for only a very short time after the reverse-bias voltage is applied. As the depletion region widens, the availability of majority carriers decreases. As more of the n and p regions become depleted of majority carriers, the electric field between the positive and negative ions increases in strength until the potential across the depletion region equals the bias voltage, Vr. At this point, the transition current essentially ceases except for a very small reverse current that can usually be neglected.

Reverse Current: The extremely small current that exists in reverse bias after the transition current dies out is caused by the minority carriers in the n and p regions that are produced by thermally generated electron-hole pairs. The small number of free minority electrons in the p region are “pushed” towards the pn junction by the negative bias voltage. When these electrons reach the wide depletion region, they “fall down the energy hill” and combine with the minority holes in the n region as valence electrons and flow towards the positive bias voltage, creating a small hole current.

The conduction band in the p region is at higher energy level than the conduction band in the n region. Therefore, the minority electrons easily in p region pass through the depletion region because they require no additional energy.

4. I-V Characteristics for pn junction diode

4.1 Forward bias:

When a forward- bias voltage is applied across a diode, a current flows in the junction. The current is called forward current and is designated by IF as shown in figure 8. With 0 V across the diode, there is no forward current. As forward bias voltage is gradually increased, the forward current and the voltage across the diode increases gradually. When the forward bias voltage is increased to a value where the voltage across the diode reaches approximately 0.7 V (barrier potential), the forward current begins to increase rapidly. On further increasing the forward bias voltage, the current increases very rapidly, but the voltage across the diode increases only gradually above 0.7 V. This small increase in the diode voltage above the barrier potential is due to the voltage drop across the internal dynamic resistance of the semiconductor material. The resistance of the forward- biased diode is not constant over the entire curve and hence, it is called dynamic resistance or ac resistance.

4.2 REVERE BIAS:

When a reverse bias voltage is applied across a diode, there is only an extremely small reverse current (Irev) through the pn junction. With 0 V across the diode, there is no reverse current. As reverse bias voltage is gradually increased, there is a very small reverse current and the voltage across the diode increases. When the applied bias voltage is increased to a value where the reverse voltage across the diode (VR) reaches the breakdown value (VBR), the reverse current begins to increase rapidly as evident from figure 9.

4.2 COMPLETE I-V CHARACTERISTIC CURVE:

Combining both the above curves for forward and reverse bias, we get the complete I-V characteristics curve for a diode shown in figure 10. IF scale is in mA, while IR scale is in µA.

Temperature Effects: For a forward bias diode, as temperature is increased, the forward current increases for a given value forward voltage. For a reverse biased diode, as temperature increases, the reverse current also increases.

5. Summary

Semiconductor growth techniques for the growth of crystal and thin films were discussed.Different growth techniques of pn junction fabrication including the physical vapor and chemical vapor deposition techniques.Forward and reverse biasing of pn junction diode including the IV characteristics of pn junction under both biasing conditions