3 MOS Capacitors

Dr. Ayushi Paliwal and Dr. Monika Tomar

1. Introduction

Metal–oxide–semiconductor (MOS) capacitors exhibit sophisticated characteristics when compared to the ordinary metal–dielectric–metal capacitors. It is the replacement of one metal electrode by a semiconductor that leads to some unique effects. The dielectric in the MOS capacitor has almost always been the silicon dioxide, or oxide, for short, so the standard term is MOS (metal–oxide– semiconductor).The MOS capacitor can be seen as a structure consisting of two heterojunctions: (1) metal–dielectric and (2) dielectric– semiconductor, where the dielectric is the silicon dioxide. It is the high quality of oxide–semiconductor interface that enables practical applications of this device structure. For decades, a device-quality oxide–semiconductor interface has been limited to one semiconductor only—silicon. It is this fact that makes silicon by far the dominant semiconductor, in spite of the fact that many other semiconductors have better bulk properties. Recently, device-quality oxide– semiconductor interfaces have been developed on silicon carbide—a wide-energy-gap semiconductor with excellent bulk properties. The problems with the interface are due to the dangling atomic bonds at the semiconductor surface that have to be electronically passivated to enable existence of mobile chargeat the semiconductor surface. There are no special effects at the metal–oxide interface. In fact, heavily doped polysilicon has been typically used in the place of metal electrode, the reason being an important technological effect that relates to the MOSFET structure.

MOS capacitors have been used in linear circuits and as the storage elements in random-access memories (RAMs) and charge-coupled devices (CCDs). The real importance of this structure, however, is that it is the central part of the most used device in electronics—the metal–oxide–semiconductor field-effect transistor (MOSFET).The metal (or heavily doped polysilicon) electrode of the MOS capacitor in a MOSFET is called the gate. Accordingly, the metal/polysilicon electrode of the MOS capacitor will be referred to as the gate, and the oxide will frequently be referred to as the gate oxide to distinguish it from oxide layers that play other roles in integrated circuits.

MOS diode is useful in the study of semiconductor surfaces, and is the core of the most important devices for VLSI-MOSFET. The schematic of the MOS diode is as follows:

2. Ideal MOS device:

Ideal MOS diode is defined as:

• At zero applied bias, the energy difference between metal work function q m and semiconductor work function q s is zero.
• Oxide is perfect insulator devoid of any charges

The energy band diagram of an ideal MOS diode under zero applied bias is shown in figure 2 below:

When applied bias is zero to an ideal MOS diode, then energy difference between the metal work function and the semiconductor wave function is zero i.e. the work function difference is zero. Thus, the work function difference for p-type semiconductor can be expressed as

For Si-SiO2 system, q  m < q  Bm

The energy band is flat when V = 0 (Flat band condition):

The only charges that exist in diode under any biasing conditions are those in semiconductors and those with equal but opposite sign on metal surface (adjacent to oxide). No carrier transport through the oxide under dc-biasing conditions, or resistivity of oxide is infinite.

When ideal MOS diode is biased (positive or negative), there are three cases arises at semiconductor surface.
Thus, three biasing conditions for an ideal MOS diode are as follows.

3. Biasing conditions of an ideal MOS diode:

Case I: For a small and negative applied voltage V < 0, fermi level on metal side is raised by an amount qV than on metal side. The schematic under this biasing condition is shown in figure 3(a) and the energy band diagram is shown in figure 3(b).

Since, m & remains unaffected by applied V, vacuum level on metal side also rise by qV. Bands near semiconductor surface are bent upward (Ev, Ei, Ec). No current flows in MOS irrespective of V; the Fermi level in semiconductor will remain constant. The vacuum level must bend up gradually to accommodate applied V (from semiconductor side). Since, oxide is assumed to be charge free, the lower edge of the oxide conduction band will bend linearly.

The negative applied bias voltage (-V) on the gate implies that negative charge on gate producing equal and opposite charges in the semiconductor by attracting holes near the oxide-semiconductor interface. Therefore, there is an enhanced concentration of holes occurs near semiconductor surface with a consequent upward bending of energy levels. [Surface accumulation condition].

We know that carrier density in the semiconductor is =(  −  )/  (3)

The upward bending of energy band causes the increase in (Ei – EF) implying enhanced concentration of holes near oxide-semiconductor interface which is called as Accumulation condition.

Case II: For a small positive applied voltage V > 0, holes are pushed away from oxide interface. Therefore, there is a formation of depletion region in semiconductor near interface, having mainly negative charged acceptor (Na) ions. [Depletion Condition]. The schematic under this biasing condition is shown in figure 4(a) and the energy band diagram is shown in figure 4(b).

Since hole concentration in depletion region is very much less than the concentration of holes in neutral region of semiconductor, separation between EF and Ev is increased at interface causing a downward bending of energy levels Ec , Ev and Ei..

The space charge per unit area in the semiconductor is [charge in depletion region which is W] = −    (4)

where W represents the width of surface depletion region, and Na is the concentration of acceptor ions in the semiconductor.

Case III: For a large positive applied voltage V >> 0, there is a downward bending of bands occurs and when Ei touches EF at surface, then semiconductor surface becomes intrinsic (np = ni). For large V, Ei crosses EF and conduction band comes closer to EF instead of valence band i.e. minority carriers (electrons) are attracted to interface, semiconductor surface contains more electrons than holes. [Surface gets inverted from p-type to the n-type]. The thin region (xi) where electrons concentration exceeds the hole concentration is called the inversion layer. The schematic under this biasing condition is shown in figure 5(a) and the energy band diagram is shown in figure 5(b).

In this biasing condition, minority carriers (ns) becomes more than majority charge carriers.The electron concentration in p-type material is

Therefore, surface of p-type is inverted. [Inversion condition].

Once, inversion occurs at the surface: Further increase in V will induce practically all additional negative charges in the incversion layer.

Therefore, electron concentration in surface space-charge region increases rapidly with applied V in narrow region 0 < x < x1, and depletion region width reaches a maximum (Wm). [Because when bands bend downward far enough for strong inversion to occur, a very small increase in band bending (corresponding to a very small increase in W) results in a large increase in Qn in the inversion layer]. Thus, under a strong inversion condition, the charge per unit area in semiconductor is

where,= −   ( ℎ           ℎ      ) (7)

Wm is the width of surface depletion region.Qn is the inversion layer charge per unit area and is negative.Here, xi << Wm.Here, n- and p- regions are separated by depletion region [like in pn junction], howeverjunction is obtained by applying field normal to surface and thus field induced junction.

4. Detailed analysis of surface space-charge region:

The electrostatic potential p, defined as zero in the bulk of semiconductor. At surface, p = sp which is surface potential.

Similarly, the hole concentration in the semiconductor as a function of is = (  − )/   and electron  concentration in semiconductor as a function of is = ( −  )/  where   > 0 where band is bend downwards.

Also, at the surface, densities are [   =   s]: = (  −  )/  (13) (from 11) and = (  −  )/  (14) (from 10) =−   /  (15) can infer that if the surface potential of p-type semiconductor in MOS device is sp < 0: ps>> ni and ns << ni Accumulation of holes (bands bends upward)(at V < 0) sp = 0 : Flat-band condition (no bending of bands) Equilibrium condition (at V = 0) Bp >sp > 0 : ps << ni Depletion of holes (bands bend downward) (at V > 0) sp =Bp : ns = pi = ni Intrinsic surface (midgap) sp > Bp : ns >> ni and ps << ni Inversion layer of electrons (bands bend downward) (at V >> 0)

e.g:

1. When hole accumulation occurs (ps > NA) implies s < 0 (from 14). => Ei (in bulk) is lower than Ei (surface) => Energy band bend upward.

2. When hole depleted: (ps < NA) =>   s > 0 (from 14) ; => energy band bend downwards INVERSION CONDITION: Surface becomes intrinsic when s = B. Therefore, onset of inversion for p-type semiconductor is given by s > B. Strong inversion occurs when minority carrier concentration at surface (ns) equals majority carrier concentration in bulk (po = NA). For p-type => ns = no and surface potential for this condition is   s (strong inversion) = 2  B (15) (from 8 and 12) i.e. when Ei at surface comes below EF as much as it is above EF in bulk.