4 Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

Dr. Ayushi Paliwal and Dr. Monika Tomar

1. Introduction

MOSFET (Metal Oxide Semiconductor Field Effect Transistor is a unipolar transistor acting as a voltage controlled device where current between the two electrodes ‘Drain’ and ‘Source’ is controlled by the applied electric field at another electrode (Gate). Here metal Gate is isolated from the semiconductor by a very thin oxide layer. The characters of metal oxide silicon field effect transistors, or MOSFETs are quite similar to those of JFETs, although there is a difference in their mechanism of production. A replacement of gate-channel p-n junction of JFET is done by a metal oxide silicon capacitors that influences the number of carriers in the channel. The carrier density in the channel is modulated by the applied gate voltage, whereas the width of the channel is hardly affected. Comparison of MOSFTE and JFET is given below:

MOSFET	JFET
It can be operated in both depletion mode and enhancement mode	It can be operated only in depletion mode
Have high input impedance, thus small input current	Relatively low input impedance
MOSFETs have higher speed of operation i.e. they respond instantaneously with a small change in gate voltage	JFETs are relatively slower

2.  Type of MOSFETs

3. Enhancement mode (E-MOSFET)

3.1 Schematic of n-channel E-MOSFET

Figure 1 shows a schematic of a n-channel E-MOSFET. It has “Metal” Gate electrode which is electrically insulated from semiconductor (n-type or p-type) by very thin layer of oxide material usually silicon dioxide. A thin layer of silicon dioxide covers the surface of silicon, which performs three functions: it acts as a protective layer for the silicon surface which ensures stable electrical behavior; it acts as an insulator for the deposition of conductors on its surface, without making electrical contact to the semiconductor; it acts as a dielectric for the capacitor formed by the gate electrode and the substrate. Gate terminal is isolated from current carrying channel, so no current flows into gate.

It consists of a p- Si substrate into which 2 heavily doped n+ region have been diffused namely Source

(S) and Drain (D). Metal contact is deposited on oxide layer that covers gap between two n+ diffusion and serves as Gate (G). Here, L is channel length [distance between two n+ region], Z is channel width, d is thickness of oxide layer, NA is acceptor doping concentration in p-type Si, Central section of device corresponds to MOS diode and Source is used as voltage reference.

3.2 Detailed operation of n-channel E-MOSFET

Case I: VG = 0

Source-to-drain electrodes corresponds to two n+- p junctions connected back to back. Device is off, when VG = 0 as there is no channel between Source and Drain.

Case II:VG > VT (Inversion condition for MOS)

Large positive gate voltage [VG > VT] has to be applied to induce a channel below oxide i.e. a surface inversion layer (accumulated electrons) is created. The electron concentration in channel enhances by increasing VG and hence channel conductance can be modulated by VG.

FOR VG > VT

Case A: For small value of +VD

Electron will flow from S to D through conducting channel. Channel acts as a resistance and ID VD (linear region). As long as VD is small, the surface potential will remain almost same throughout channel (i.e. near source and drain regions). The electron concentration will remain same and channel behaves as resistor having

Where, Qn < 0, is the space charge per unit area of inversion layer (or channel) and Z is the channel width.

Case B: For moderate value of +VD

With increase in VD, potential will distribute throughout the channel. Potential difference between G and inversion layer will be more near S and very less near D. Thus, electron concentration (Qn) in channel will be relatively less near D, and hence channel resistance increases. I-V curve will bend downward from initial linear variation.

Case C: For large VD If VD further increases (VDsat), the potential drop across oxide near drain will continue to decrease, and may until it falls below the value required to maintain an inversion layer, i.e. width of inversion layer xi at y = L reduced to zero [known as Pinch off point]. At this condition, Drain gets isolated from conducting channel (inversion layer) by a depletion region. The ID will then saturate to a constant value Idsat at VD = VDsat.

Case D: As VD > VDsat, ID remains as IDsat. The pinch off point P will move towards Source, and effective channel length (L ) will decrease. However, the potential at P will remain at VDsat, and additional voltage in excess of VDsat will drop across depletion region. Thus, number of carriers arriving at point P from Source and hence current flowing from D to S remains the constant.

If VG or VGS increases (For Fixed VD), leads to increases in the inversion layer and thus charge Qn.

Therefore, channel resistance decreases or ID increases for a given VD. The pinch off will occur at a higher value of VD.

3.3 Study of I-V relationship for n-channel E-MOSFET

Consider ideal condition and following assumptions

• Ideal MOS structure [no charge in oxide and no difference in work functions of Gate and Semiconductors, ms = 0]
• Current flow in one dimention (i.e. in channel only). No current flows from Channel to Gate.
• Electron mobility in Inversion layer (channel) is constant and is independent of electric field.
• Doping in the semiconductor in the channel region is uniform.
• Reverse-leakage current is negligibly small.
• Transverse electric field (perpendicular to the current flow) at edge of the depletion region in channel is much larger than the longitudinal electric field (parallel to current flow).

4. Theoretical characteristics of a MOSFET

The relationship between voltages applied to the MOSFET electrodes and the current that flows from source to the drain, is described in this section. An ideal model of an n-channel MOSFET is shown in figure 5. Consider strong inversion condition [No drain current flow in a MOS so system in thermal equilibrium i.e. VD = 0], the surface potential.

Consider n-channel MOSFET

Total charge induced in semiconductor at y

where Qn is the charge per unit area in inversion region and Qsc is the charge per unit area in depletion region.

Applied VG is partly divided in oxide layer and semiconductor  as

where, Vo is voltage drop across oxide layer.In case of non ideal MOS capacitor, with flat-band voltage VFB, equation (3) is modified as

At onset of inversion,

Under practical operating condition, space charge region in MOS transistor is not in equilibrium i.e. when VD > 0, the surface potential will increase with y [due to potential distribution in semiconductor]. If V(y) is channel potential at any point y for a drain voltage VD, then to a good approximation the surface potential for strong inversion is

Also using depletion approximation, the charge per unit area at strong inversion (as calculated while discussing MOS diode) is

For ideal MOSFET remove the contribution from VFB in equation (10) Now, discussing above equation (10) in different conditions (A) LINEAR REGION:For small VD such that VD << VG – VT  or

By plotting ID versus VG (for small VD), VT can be obtained from linear extrapolation to VG axis.For n-channel MOSFET, VFB is small negative and other two terms of equation (13) are positive, => VT > 0 (turn- on voltage).

From equation (12) => ID VD for small VD. In linear region from equation (12) we have

(B) SATURATION REGION:

When VD >Vsat, then at Drain end the net voltage across MOS is less than or equal to VT i.e. number of mobile electrons in channel at the Drain are reduced drastically(Pinch off point).

At Source side: V(y) =0 ,Qn(y) = Qn at y = 0

At Drain side: V(y) = VDsat , Qn(y) = 0 at y = L

Putting source side condition in equation (7) i.e. for Qn (y), we have

Find out VDsat from equation (16) and substitute VD = VDsat in equation (10), we can obtain expression for ID in saturation region i.e. IDsat.

However, when NA is very low and oxide layer thickness is small (i.e. Co is large), then << 1 (from 17). Here voltage drop in oxide is negligibly small compared to 2 B.

Thus equation (16) becomes

Thus Channel conductance (gD) in linear region (eqn. 14) is same as Trans Conductance (gm) in saturation region (eqn. 20) for MOSFET.

5. Construction of n and p-channel Depletion mode MOSFET

Figure 6 shows the n-channel D-MOSFET. Drain (D) and Source (S) leads connect to the to n+-doped regions via an n-channel. n-channel is connected to the Gate (G) via a thin insulating layer of SiO2. The n-doped material lies on a p-doped substrate that may have an additional terminal connection called SS.

The p-channel Depletion mode MOSFET is similar to the n-channel except that channel is p-type and the voltage polarities and current directions are reversed

7. Summary

• Schematic of enhancement mode MOSFET (E-MOSFET)
• Detailed operation of n-channel MOSFET
• Study of IV characteristics for E-MOSFET
• Construction of n and p-channel Depletion mode MOSFET
• Frequency limit for MOSFET