8 CMOS Technology

Dr. Ayushi Paliwal and Dr. Monika Tomar

1. Introduction

Modern CMOS processing is a complicated process and requires lot of understanding the processing technology of CMOS. A fair question from a designer would be “Why do I care how transistors are made?” In many cases, if designers understand the physical process, they will comprehend the reason for the underlying design rules and in turn use this knowledge to create a better design. Understanding the manufacturing steps is also important when debugging some difficult chip failures and improving yield. Fabrication plants, or fabs, are enormously expensive to develop and operate. In the early days of the semiconductor industry, a few bright physicists and engineers could bring up a fabrication facility in an industrial building at a modest cost and most companies did their own manufacturing. Now, a fab processing 300 mm wafers in a 45 nm process costs about $3 billion. The research and development underlying the technology costs another $2.4 billion. Only a handful of companies in the world have the sales volumes to justify such a large investment. Even these companies are forming consortia to share the costs of technology development with their market rivals. Silicon in its pure or intrinsic state is a semiconductor, having bulk electrical resistance somewhere between that of a conductor and an insulator. The conductivity of silicon can be raised by several orders of magnitude by introducing impurity atoms into the silicon crystal lattice. These dopants can supply either free electrons or holes. Group III impurity elements such as boron that use up electrons are referred to as acceptors because they accept some of the electrons already in the silicon, leaving holes. Similarly, Group V donor elements such as arsenic and phosphorous provide electrons. Silicon that contains a majority of donors is known as n-type, while silicon that contains a majority of acceptors is known as p-type. When n-type and p-type materials are brought together, the region where the silicon changes from n-type to p-type is called a junction. By arranging junctions in certain physical structures and combining them with wires and insulators, various semiconductor devices can be constructed. Over the years, silicon semiconductor processing has evolved sophisticated techniques for building these junctions and other insulating and conducting structures.

2. CMOS technologies

The main CMOS technologies are:

(a) n-well process

(b) p-well process

(c) twin-well process

(d) triple-well process

It is well known that p-well processes preceded n-well processes. So, focus is on a p-well process where p-well is formed containing the nMOS transistors and the pMOS transistor is placed in the n-type substrate. There are enormous advanced techniques making fabrication of good pMOS transistors in the n-well to be possible and similarly in n-well process excellent nMOS transistors can be fabricated in the p-type substrate. Twin-well process accompanied the emergence of n-well processes which allows the optimization of each transistor type. Last type of CMOS technology is a triple-well process which consist of a third well to provide good isolation between analog and digital blocks in mixed-signal chips. This further provides a good isolation of high-density dynamic memory from logic.

2.1 Wafer formation

A wafer (or a disk of silicon for example) is the basic raw material used in modern semiconductor fabrication processes whose diameter varies roughly from 75 mm to 300 mm and less than 1 mm thick. These wafers are cut from ingots of single-crystal silicon and these crystals requires a special technique to pull the single crystal from a crucible melt of pure molten silicon. This special technique is referred to as Czochralski method and is most exploited method for producing single-crystal material. The required electrical properties can be achieved by adding controlled amount of impurities to the melt. This method requires a seed crystal which is dipped into the melt to initiate crystal growth and the silicon ingot takes on the same crystal orientation as the seed. In order to melt the silicon to molten form, a heater is provided controlled by radio-frequency induction which maintains the temperature a few degree above the melting point of silicon (1425 C). The atmosphere is typically helium or argon to prevent the silicon from oxidizing. The whole assembly is rotated and simultaneously the seed is gradually withdrawn vertically from the melt. The molten silicon attaches itself to the seed and recrystallizes as it is withdrawn. The seed withdrawal and rotation rates determine the diameter of the ingot.

2.2 Photolithography

It is being recalled that there are particular regions of dopants, polysilicon, metal, and contacts which are defined using masks. This patterning is achieved by a process called as photolithography, from the Greek photo (light), lithos (stone), and graphe (picture), which literally means “carving pictures in stone using light”. Photoresist is primarily used for defining areas of interest (i.e., where we want material to be present or absent) on a wafer. The basic phenomenon includes the coating of the wafer with the photoresist which is further subjected to selective illumination through the photomask. After the initial patterning of photoresist, other barrier layers such as polycrystalline silicon, silicon dioxide, or silicon nitride can be used as physical masks on the chip. A photomask is constructed with chromium (chrome) covered quartz glass.

Basically, UV light source is used to expose the photoresist and figure 1 illustrates the lithography process in detail. This consists of a photomask having chrome where light should be blocked and the UV light floods the mask from the backside. This UV light while passing through the clear sections of the mask used to expose the organic photoresist (PR) which is being coated on the wafer. The unexposed photoresist is removed by dissolving it in a developer solvent, leaving islands of insoluble exposed photoresist. This is termed a negative photoresist. Whereas a positive resist becomes soluble when exposed to UV and these type of resists provide higher resolution than negative resists, but are less sensitive to light.

The wavelength of the light source influences the minimum feature size that can be printed. Let us define the minimum pitch (width + spacing) of a process to be 2b. The resolution of a lens depends on the wavelength of the light and the numerical aperture NA of the lens:

where n is the refractive index of the medium (different for different media), and α is the angle of acceptance of the lens. Here, there is another parameter i.e. k1 which depends on the coherence of the light, antireflective coatings, photoresist parameters, and resolution enhancement techniques. Another crucial parameter is the depth of focus which is given by 2 = 2 where k2 ranges from 0.5 to 1. Advanced lithography systems with short wavelengths and large numerical apertures have a very shallow depth of focus, requiring that the surface of the wafer be maintained extremely flat.

2.9 Well and Channel Formation

The following are main CMOS technologies: n-well process, p-well process, twin-well process and triple-well process. The formation of wells and other features require regions of doped silicon. There are various techniques to introduce varying proportions of donor and acceptor dopants i.e. epitaxy, deposition, or implantation.

In the technique of epitaxy, a silicon wafer surface is subjected to an elevated temperature and source of dopant material in order to grow a single-crystal film on the silicon surface. This is a suitable to produce a layer of silicon with fewer defects than the native wafer surface and also can help prevent latchup.

Another is the technique of deposition where a dopant material is placed onto the silicon surface and then driving it into the bulk using a thermal diffusion step. This can be used to build deep junctions. Chemical vapor deposition (CVD) is used for the deposition where a product is deposited on the silicon in the ambience of heated gases which reacts in the vicinity of the wafer. CVD is also used to lay down thin films of material later in the CMOS process.

Ion implantation involves colliding the silicon substrate with highly energized donor or acceptor atoms where they travel below the surface of the silicon resulting in regions with varying doping concentrations. At elevated temperature (>800 °C) diffusion occurs between silicon regions having different densities of impurities, with impurities tending to diffuse from areas of high concentration to areas of low concentration. Therefore, it is important to keep the remaining process steps at as low a temperature as possible once the doped areas have been put into place. However, a high-temperature annealing step is often performed after ion implantation to redistribute dopants more uniformly. The placement of ions is a random process, so doping levels cannot be perfectly controlled, especially in tiny structures with relatively small numbers of dopant atoms. Statistical dopant fluctuations lead to variations in the threshold voltage.

The primary step in CMOS processes is to define the well regions. In a triple-well process, high energy of the order of MeV ion implantation is used to create a deep n-well into the p-type substrate. This further prevents the possibility of thermal cycling (i.e., the wafers do not have to be raised significantly in temperature), which improves throughput and reliability. For instance, a 2–3 MeV implantation can yield a 2.5–3.5 m deep n-well and has a peak dopant concentration just under the surface called as retrograde well. This can enhance device performance by providing improved latchup characteristics and reduced susceptibility to vertical punch-through. A thick (3.5–5.5 m) resist has to be used to block the high energy implantation where no well should be formed. Thick resists and deep implants necessarily lead to fairly coarse feature dimensions for wells, compared to the minimum feature size. Shallower n-well and p-well regions are then implanted. After the wells have been formed, the doping levels can be adjusted (using a threshold implant) to set the desired threshold voltages for both nMOS and pMOS transistors. With multiple threshold implant masks, multiple Vt options can be provided on the same chip. For a given gate and substrate material, the threshold voltage depends on the doping level in the substrate (NA), the oxide thickness (tox), and the surface state charge (Qfc). The implant can affect both NA and Qfc and hence Vt . Figure 2 shows a typical triple-well structure. As discussed, the nMOS transistor is situated in the p-well located in the deep n-well. Other nMOS transistors could be built in different p-wells so that they do not share the same body node. Transistors in a p-well in a triple-well process will have different characteristics than transistors in the substrate because of the different doping levels.

The pMOS transistors are located in the shallow (normal) n-well. In the case of a twin-well process, only one mask need be defined because the other well by definition is its complement. Triple-well processes have to define at least two masks, one for the deep well and the other for either n-well or p-well. Transistors near the edge of a retrograde well (e.g., within about 1 m) may have different threshold voltages than those far from the edge because ions scatter off the photoresist mask into the edge of the well, as shown in Figure 3. This is called the well-edge proximity effect.

2.10 Silicon Dioxide (SiO2)

Reliable formation of SiO2 is crucial for various manufacturing techniques used to make silicon integrated circuits. In fact, unlike competing materials, silicon has dominated the industry because it has an easily processable oxide (i.e., it can be grown and etched). Different thicknesses of SiO2 are required for a particular application. Thin oxides are required for transistor gates; thicker oxides might be required for higher voltage devices, while even thicker oxide layers might be required to ensure that transistors are not formed unintentionally in the silicon beneath polysilicon.

Oxidation of silicon is achieved by heating silicon wafers in an oxidizing atmosphere and there various techniques as follows:

(i) Wet oxidation––when the oxidizing atmosphere contains water vapor having the temperature between 900 °C and 1000 °C. This is also called pyrogenic oxidation when a 2:1 mixture of hydrogen and oxygen is used. Wet oxidation is a rapid process.

(ii) Dry oxidation––when the oxidizing atmosphere is pure oxygen and temperatures are in the region of 1200 °C to achieve an acceptable growth rate. It is used to form thin, highly controlled gate oxides, while wet oxidation may be used to form thick field oxides.

(iii) Atomic layer deposition (ALD)––when a thin chemical layer (material A) is attached to a surface and then a chemical (material B) is introduced to produce a thin layer of the required layer (i.e., SiO2––this can also be used for other various dielectrics and metals). The process is then repeated and the required layer is built up layer by layer.

2.11 Isolation

Individual devices in a CMOS process need to be isolated from one another so that they do not have unexpected interactions. In particular, channels should only be inverted beneath transistor gates over the active area; wires running elsewhere shouldn’t create parasitic MOS channels. Moreover, the source/drain diffusions of unrelated transistors should not interfere with each other. The transistor gate consists of a thin gate oxide layer. Elsewhere, a thicker layer of field oxide separates polysilicon and metal wires from the substrate. The source and drain of the transistors form reverse-biased p–n junctions with the substrate or well, isolating them from their neighbors. The thick oxide used to be formed by a process called Local Oxidation of Silicon (LOCOS). A problem with LOCOS-based processes is the transition between thick and thin oxide, which extended some distance laterally to form a so-called bird’s beak. The lateral distance is proportional to the oxide thickness, which limits the packing density of transistors. Starting around the 0.35 m node, shallow trench isolation (STI) was introduced to avoid the problems with LOCOS. STI forms insulating trenches of SiO2 surrounding the transistors (everywhere except the active area). The trench width is independent of its depth, so transistors can be packed as closely as the lithography permits. The trenches isolate the wires from the substrate, preventing unwanted channel formation. They also reduce the sidewall capacitance and junction leakage current of the source and drain.

Figure 4 shows that STI starts with a pad oxide and a silicon nitride layer, which act as the masking layers. Openings in the pad oxide are then used to etch into the well or substrate region (this process can also be used for source/drain diffusion) and a liner oxide is then grown to cover the exposed silicon (Figure 4(b)). The trenches are filled with SiO2 or other fillers using CVD that does not consume the underlying silicon (Figure 4(c)). Now in order to planarize the structure, the Chemical Mechanical Polishing (CMP) step is exploited to remove the pad oxide and nitride (Figure 4(d)). CMP, as its name suggests, combines a mechanical grinding action in which the rotating wafer is contacted by a stationary polishing head while an abrasive mixture is applied. The mixture also reacts chemically with the surface to aid in the polishing action.

2.12     Gate Oxide and Gate and Source/Drain Formations

The next step in the process is to form the gate oxide for the transistors. As mentioned, this is most commonly in the form of silicon dioxide (SiO2). In the case of STI-defined source/drain regions, the gate oxide is grown on top of the planarized structure. This is shown in Silicon Nitride Well or Active Substrate or Buried Oxide (a) Trench Etch (b) Liner Oxidation (c) Fill Trench with Dielectric (d) CMP for Planarization Trench Pad Oxide Substrate n-well p-well n-well n-well n-well p-well Trench Oxide.

Now, a polysilicon is formed when silicon is deposited on SiO2 or other surfaces without crystal orientation whose crystal domain sizes can be controlled by annealing process. Undoped polysilicon has high resistivity which can be reduced by implanting it with dopants and/or combining it with a refractory metal. The polysilicon gate serves as a mask to allow precise alignment of the source and drain on either side of the gate. This process is called a self-aligned polysilicon gate process. Aluminum could not be used because it would melt during formation of the source and drain. The steps to define the gate, source, and drain in a self-aligned polysilicon gate are as follows: grow gate oxide wherever transistors are required (area = source + drain + gate)–– elsewhere there will be thick oxide or trench isolation (Figure 5(a)), deposit polysilicon on chip (Figure 5(b)) and pattern polysilicon (both gates and interconnect) (Figure 5(c)). Finally, etch exposed gate oxide—i.e., the area of gate oxide where transistors are required that was not covered by polysilicon; at this stage, the chip has windows down to the well or substrate wherever a source/drain diffusion is required (Figure 5(d)) and Implant pMOS and nMOS source/drain regions (Figure 5(e))

2.13     Contacts and Metallization

Contact cuts are made to source, drain, and gate according to the contact mask which are holes etched in the dielectric after the source/drain step. Older processes commonly use aluminum (Al) for wires, although newer ones offer copper (Cu) for lower resistance. Tungsten (W) can be used as a plug to fill the contact holes (to alleviate problems of aluminum not conforming to small contacts). In some processes, the tungsten can also be used as a local interconnect layer. Metallization is the process of building wires to connect the devices. As mentioned previously, conventional metallization uses aluminum. Aluminum can be deposited either by evaporation or sputtering. Evaporation involves the deposition of vaporized aluminum on the wafer in a vacuum chamber by passing a high electrical current. Advanced form of evaporation that suffers less from contamination is exploiting a focused electron beam to evaporate the aluminum. Sputtering is achieved by generating a gas plasma by ionizing an inert gas using an RF or DC electric field. The ions are focused on an aluminum target and the plasma dislodges metal atoms, which are then deposited on the wafer. Wet or dry etching can be used to remove unwanted metal.

2.14 Passivation and metrology

The final processing step is to add a protective glass layer called passivation or overglass that prevents the ingress of contaminants. Openings in the passivation layer, called overglass cuts, allow connection to I/O pads and test probe points if needed. After passivation, further steps can be performed such as bumping, which allows the chip to be directly connected to a circuit board using plated solder bumps in the pad openings.

Metrology is the science of measuring. Everything that is built in a semiconductor process has to be measured to give feedback to the manufacturing process. This ranges from simple optical measurements of line widths to advanced techniques to measure thin films and defects such as voids in copper interconnect. A natural requirement exists for in situ real-time measurements so that the manufacturing process can be controlled in a direct feedback manner. Optical microscopes are used to observe large structures and defects, and Scanning electron microscopy (SEM) is used to observe very small features. Another technique is Energy Dispersive Spectroscopy (EDX) bombards a circuit with electrons causing x-ray emission also used for imaging as well. A Transmission Electron Microscope (TEM), which observes the results of passing electrons through a sample (rather than bouncing them off the sample), is sometimes also used to measure structures.

3. Summary

Various CMOS technologies

Different steps in CMOS fabrication like wafer formation, photolithography, well and channel formation, Silicon Dioxide (SiO2), Isolation, Gate Oxide and Gate and Source/Drain Formations , Contacts and Metallization, Passivation and metrology