2 Basics of BJT and JFET

Dr. Monika Tomar and Dr. Ayushi Paliwal

1. Introduction

The modern era of semiconductor electronics was ushered in by the invention of the bipolar transistor in 1948 by Bardeen, Brattain, and Shockley at the Bell Telephone Laboratories. This device, along with its field-effect counterpart, has had an enormous impact on virtually every area of modern life. In this module, we will learn about the operation, applications, and fabrication of the field-effect transistor (FET). The field-effect transistor comes in several forms. In a junction FET (called a JFET) the control (gate) voltage varies the depletion width of a reverse biased p-n junction. A similar device results if the junction is replaced by a Schottky barrier (metal-semiconductor FET, called a MESFET). Alternatively, the metal gate electrode may be separated from the semiconductor by an insulator (metal-insulator-semiconductorFET, called a MISFET). A common special case of this type uses an oxide layer as the insulator (MOSFET). We have found that two dominant features of p-n junctions are the injection of minority carriers with forward bias and a variation of the depletion width W with reverse bias. These two p-n junction properties are used in two important types of transistors. The bipolar junction transistor (BJT) uses the injection of minority carriers across a forward-biased junction, and the junction field-effect transistor discussed in this chapter depends on control of a junction depletion width under reverse bias. The FET is a majority carrier device, and is therefore often called a unipolar transistor. The BJT, on the other hand, operates by the injection and collection of minority carriers. Since the action of both electrons and holes is important in this device, it is called a bipolar transistor. Like its bipolar counterpart, the FET is a three-terminal device in which the current through two terminals is controlled at the third. Unlike the BJT, however, field-effect devices are controlled by a voltage at the third terminal rather than by a current. The history of BJTs and FETs is rather interesting. It was the FET that was proposed first in 1930 by Lilienfeld, but he never got it to work because he did not fully appreciate the role of surface defects or surface states. In the process of trying to demonstrate experimentally such a field-effect transistor, Bardeen and Brattain somewhat serendipitously invented the first bipolar transistor, the Ge point contact transistor. This major breakthrough was rapidly followed by Shockley’s extension of the concept to the BJT. It was only much later, after the problem of surface states was resolved by growing an oxide insulator on Si, that the first MOSFET was demonstrated in 1960 by Kahng and Atalla. Although the BJT reigned supreme in the early days of semiconductor integrated electronics, it has been gradually supplanted in most applications by the Si MOSFET. The main reason is, unlike BJTs, the various types of FET are characterized by a high input impedance, since the control voltage is applied to a reverse-biased junction or Schottky barrier, or across an insulator. These devices are particularly well suited for controlled switching between a conducting state and a nonconducting state, and are therefore useful in digital circuits. They are also suitable for integration of many devices on a single chip.

2. Junction field effect transistors (JFET)

The conduction path through a semiconductor is reduced due to voltage-dependent width of a reverse-biased p-n junction, which results in alteration of the semiconductor’s resistance. It consists of a bar semiconductor with ohmic contacts at each end, i.e. source (S) and drain (D) as shown in figure 1. The path between source and drain, is for the current flow, and is called channel. There is an intrusion of two p-n junctions opposite each other, in the channel, which is called as gate (G). if the channel is n-type, then it is called as n-channel JFET and if p-type it is referred as p-channel JFET. Their structure and symbols are clearly depicted in figure 1.

The p-n junctions restrict the cross sectional area of the channel, because the transition region of p-n junction lacks any mobile charge carrier. The width of the transition region depends upon the voltage applied to it, so the drain current varies according to the variation in gate-source voltage (figure 1).

2.1 Operation of JFET (n-channel)

Figure2 shows the principal n-channel JFET structure. Where the device current is due to flow of electrons from the source n+ region, through the n-type layer called the channel, into the n+ drain. The n-channel is sandwiched between top and bottom p+ layers, whose separation determines the channel thickness. The top and bottom p+ layers create p-n junctions with the n-type channel. The depletion layers associated with these junctions predominantly expand into the n-layer because its doping level is much lower than the doping of the p+ regions. The dotted lines in Figure 2 show the edges of the depletion layers associated with the upper and lower p-n junctions. It is the distance between the two depletion layers, not the separation between the p-n junctions themselves, that is equal to the electrically effective channel thickness. The upper and the lower p-n junctions can be reverse-biased,which increases the depletion-layer widths, thereby reducing the channel thickness and thus reducing the current that can flow through the channel. In the extreme case, the depletion layers extend over the whole thickness of the n-type layer, thereby reducing the electrically effective channel thickness to zero and thus reducing the JFET current to zero. This shows that the current can be controlled by the value of negative voltage applied to the upper and/or lower p+ layer. Either of the two p+ layers can be used as a gate. The voltage applied between Gate and Source terminal i.e. VGS or VG 0 i.e. it is reverse biased whereas voltage applied between Drain and Source terminal i.e. VDS or VD 0 i.e. it is forward biased. With the application of drain voltage i.e. as VD 0, drain current flows (i.e. ID ) for VGS = 0. Now, by applying VGS, the width channel varies affecting the flow of charge carriers. Thus, ID is influenced by the application electric field i.e. VGS , hence known as field effect transistor.

However, the most practical form, substrate is directly connected to the source, which ensures zero bias.The following diagram gives practical form of construction in silicon as shown in figure 3.

In this type, all the terminals are diffused into the channel material. There is a thin n-type channel, that is laid on a much thicker p-type substrate that provides mechanical strength. As there is p-n junction between the channel and substrate and channel and gate, it provides a non-conducting walls to the channel, as long as they are not forward biased by more than 0.5V (i.e. when the channel is widest). The channel narrows when there is increase in reverse bias on either p-region. The output signal current is made to flow between source and drain by applying a D.C. reverse bias plus any signal voltages between channel and substrate. However on other hand, an electron current can easily flow through the n-n+ junctions of source and drain.

2.2 I-V characteristics of n-channel JFET

When only a negative gate-source voltage VGS is applied, leaving an open circuit at drain or connected to the source, it reverse biases gate p-n junction and so causes transition region to widen, thus reducing the width of the channel. At a particular value of VGS, the gate widens through the p-region on the other side, cutting off the channel. The voltage at which it occurs, is called pinch-off voltage, VP for a particular device and at this value, no current flows through the channel even if drain-source voltage (VDS) is applied. VP is difficult to control in production, so it varies between devices. The behavior of device becomes more complicated when various voltages are applied to both gate and drain.

Case (1): Linear region:

Figure 4 shows JFET under the first condition which discusses the linear region. Here channel behaves as a resistor with resistance R0. The depletion width remains almost constant across the entire channel, and ID VD

If a small VD is applied, a small ID flows ID ~ VD/R0 (1) ID increases linearly with increase in VD

One expects that the gate transition regions would extend right through the channel as the drain voltage is increased further, thus, cutting off the current completely, as also predicted by Shockley, the inventor of JFET. The channel is pinched rather than cut off. Because of the steady voltage drop along the channel, it tapers from one end to the other, because there is a steady voltage drop along it. The drain current flowing through the channel multiplied by the channel resistance between the source and any point along the channel, relative to the source, gives voltage at that point. So, there is no voltage drop along the channel, if the current were cut off and all points along it would remain at the source voltage, and there would be no decrease in the channel width from its value at the source end, so the current would not be cutoff. The solution to this paradox is that the channel is almost cut off at the drain end of the channel. The channel width keeps on becoming narrower, as the drain voltage VD is increased, to a point until which, it is ‘pinched off’, which means that the current rises asymptotically to a final value, which increases only slowly as the drain voltage increases further. The drain-gate voltage at which it occurs, is the pinch-off voltage VP, the voltage across the gate p-n junction which causes it to widen right across the channel. Then it reaches a state of steadiness, in which just sufficient channel is left to pass the current needed to produce a voltage drop along the channel equal to this pinch-off voltage. So, it turns out to be a self-adjusting process.

Pinch Off Condition:

The JFET under pinch off condition is shown in figure 5.

• As VD increases, the gate to channel pn junction is reverse biased so that the depletion width increases

• Width of depletion region (W) is more towards Drain in comparison to that at source. Average area of  channel decreases for current flow. Therefore, channel resistance increases and current increases at slower rate.

• With further increase in VD, a point is reached (VD = VDsat) where two depletion regions meet near the drain.

• Channel near the drain gets “pinched off”.

• Source and drain are isolated from each other by depletion region.

Case (2): Saturation region:

The region of operation beyond the pinch-off voltage is called the saturation region even though the current does not quite saturate. For different constant values of gate-source voltage, similar curves to that in figure 6 can be drawn. The larger the reverse bias on the gate junction the smaller the drain voltage needed to cause pinch-off.

Applying VGS < 0V

• When a reverse bias VG is applied at gate, depletion region of p+-n junction becomes more wider (W increases), and cross-sectional area of channel (A) is reduced.
• For even smaller VD, the channel resistance will be higher, because area available for current flow reduces due to VG.
• ID reduces in comparison to value of ID at VG=0. This condition is shown in figure 7.

2.3 I-V CHARACTERISTICS OF JFET

• Linear region: VGS = 0, with increase in small VDS (small depletion region), the current ID increase linearly and JFET act as the voltage controlled resistor.
• Non linear region: for moderate VDS < VDsat, depletion width increases, average channel area decreases, channel resistance increases. Thus, ID increases at slower rate with VDS for given VGS.
• Pinch off region: VGS is made sufficiently negative of VDS = VDsat such that drain and source are isolated by depletion width and constant ID flows due to injected charge carriers.
• Saturation region: VDS>VDsat and |VGS| >|VP|. The drain current ID is constant with VDS for a given value of VGS.

3. Theoretical characteristics of a JFET

The cross section of a JFET is shown in figure 9, with clearly identified variables. The approximate d.c.characteristics of a device can be calculated as follows:

If the p-type gates of the n-channel JFET are relatively doped, the p-n junctions between gates and channel must be abrupt. This is required for the proportionality of transition region width Wx, at a distance x from the source, with the square root of the applied voltage at that point.

Thus,

Here, Vx is reverse bias voltage across each transition region at a distance x from the source end of the channel, Nd is the doping density of the channel, ε is permittivity of the silicon and q is the electronic charge.

Since, VGS is negative voltage for n-channel, Vx= -VGS at x=0 and reaches maximum value of VDS-VGS at x=L. at the pinch-off voltage, VP, Wx≈a, so

As VDS is increased beyond pinch-off, ID does not remain constant because the channel shortens as VDS increases. The rate of increase is proportional to ID, so straight portions of characteristic curves can be extrapolated back to a voltage of -1/λ. From the geometry of figure 4, for output conductances, go at any operating point are given by the slopes of the characteristics.

The transconductance increases as the separation between adjacent lines in figure 4 and 6 increases with VDS , although it is generally enough to assume that gm in saturation is the same as in pinch-off. Using geometry of figure 4 to drive an expression for the increase of gm with VDS, for a particular VGS,

4. Summary

Structure of n-channel and p-channel JFET Operation of n-channel JFET

IV characteristics of JFET

Theoretical description of IV relationship for JFET Low frequency small signal model of JFET