{"id":66,"date":"2018-07-26T09:40:28","date_gmt":"2018-07-26T09:40:28","guid":{"rendered":"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/?post_type=chapter&p=66"},"modified":"2018-08-10T10:40:20","modified_gmt":"2018-08-10T10:40:20","slug":"microcontrollers-and-embedded-processors-2","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/chapter\/microcontrollers-and-embedded-processors-2\/","title":{"rendered":"Microcontrollers and Embedded Processors"},"content":{"raw":"
\r\n\r\n \r\n

In this lecture, Instruction set of 8051 microcontroller will be discussed in detail. Arithmetic and logical instructions, and control transfer instructions will be discussed with examples.<\/p>\r\n \r\n\r\n1.Instruction set<\/strong>\r\n\r\n \r\n

The process of writing program for the microcontroller mainly consists of giving instructions (commands) in the specific order in which they should be executed in order to carry out a specific task. As digital circuit cannot \u201cunderstand\u201d what for example an instruction \u201cif the push button is pressed- turn the light on\u201d means, then a certain number of simpler and precisely defined orders that decoder can recognize must be used. All commands are known as INSTRUCTION SET. All microcontrollers compatible with the 8051 have a total of 255 instructions.<\/p>\r\n \r\n

In these 255 instructions, many instructions are considered to be \u201cdifferent\u201d, even though they perform the same operation, so there are only 111 truly different commands. For example: ADD A,R0, ADD A,R1, ... ADD A,R7 are instructions that perform the same operation (addition of the accumulator and register). Since there are 8 such registers, each instruction is counted separately. Taking into account that all instructions perform only 53 operations (addition, subtraction, copy etc.) and most of them are rarely used in practice, there are actually 20-30 abbreviations to be learned, which is acceptable.<\/p>\r\n \r\n\r\n1.1 Types of instructions<\/strong>\r\n\r\n \r\n\r\nDepending on the operation that they perform, the instructions are divided into several groups:\r\n\r\n \r\n\r\n\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Arithmetic Instructions\r\n\r\n\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Branch Instructions\r\n\r\n\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Data Transfer Instructions\r\n\r\n\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Logic Instructions and\r\n\r\n\u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Bit-oriented Instructions.\r\n\r\n \r\n

The first part of each instruction, called MNEMONIC refers to the operation an instruction performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of operation being executed. For example:<\/p>\r\n \r\n\r\nADD A, R0 - ADD mnemonic (A, R0- operands registers)\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\n1.1.1 Arithmetic Instructions<\/em><\/strong>\r\n\r\n \r\n

Arithmetic instructions perform addition, subtraction, multiplication, division, increment and decrement operations. After execution, the result is stored in the first operand. For example: ADD<\/em> A,R1 - The result of addition (A+R1) will be stored in the accumulator.<\/em><\/p>\r\n \r\n\r\nTable .1 Execution Table for Arithmetic instructions\r\n\r\n \r\n\r\n\"\"\r\n\r\n \r\n

From Table.1 it is evident that always one of the operand is stored in accumulator. Addition is done through ADD and ADDC instruction. Addition with carry is needed when doing multiple addition. Subtraction is always done with borrow using SUBB instruction. Increment and decrement by one bit can be done with INC and DEC instructions. The DA A instruction is the decimal adjust used for BCD addition.<\/p>\r\n \r\n

The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16-bit product into the concatenated B and Accumulator registers. The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quotient in the Accumulator, and the 8-bit remainder in the B register.<\/p>\r\n \r\n\r\nExamples for addition and subtraction:\r\n\r\n \r\n\r\nADD A,<src-byte>\r\n\r\nAssume A=09h and R0=07h\r\n\r\nADD A,R0 ; (A) \u2190 (A) + (R0), A=10h<\/strong>\r\n\r\nADDC A,Rn ; (A) \u2190 (A) + (C) + (Rn)<\/strong>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\nIn the ADDC instruction of previous example if the carry bit is 1 then 10h+1 is 11h and that is stored in Accumulator.\r\n\r\nSUBB A,<src-byte>\r\n\r\nAssume A=09h, R0=07h, carry flag=1\r\n\r\nSUBB A,R0 ; (A) \u2190 (A) - (C) - (R0) , A=1<\/strong>\r\n\r\n \r\n\r\nExamples for multiplication and division :\r\n\r\n \r\n\r\nAssume A=09h,B=02h\r\n\r\n \r\n\r\n\u2022\u00a0MUL AB ; (A)9 \u2190 (A) X (B)<\/strong>\r\n\r\n(B)2,\u00a0 A=12h,B=00h\r\n\r\nMultiplying A and B gives 18 in decimal and in hexadecimal it is 12h. Here, LSB is stored in A register and MSB is stored in B register. There is no overflow in the above instruction, if there is overflow then those values are stored in B register.\r\n\r\n \r\n\r\n\u2022\u00a0DIV AB ; (A)9 \u2190 (A)\/(B)<\/strong>\r\n\r\n \r\n\r\n(B)2 , A=04h,B=01h\r\n\r\nDivision of A and B gives quotient as 4 and remainder as 1. A holds the quotient and B holds the remainder.\r\n\r\n \r\n\r\n1.1.2. Logical Instruction<\/em><\/strong>\r\n\r\n \r\n

Logic instructions perform logic operations upon corresponding bits of two registers. After execution, the result is stored in the first operand. These instructions perform basic logic operations such as OR,AND,XOR ,complement and rotate operations.<\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n\"\"\r\n\r\n \r\n

All logical instructions are listed in Table.2. Accumulator holds one of the operand always. ANL performs the logical AND operation. OR operation is performed through ORL instruction. XOR operation is done with XRL instruction. Reset to zero is done with CLR instruction. Complement is done with CLP. In assembly code rotation of data is also possible. Rotate left, rotate right can be done with accumulator content through RL and RR instructions. RLC and RRC will take care about rotating accumulator data with carry. SWAP will swap lower and upper nibbles of accumulator data. The execution time for all these instructions are listed in Table.2.<\/p>\r\n \r\n\r\n \r\n\r\nExample for Logical AND operation :\r\n\r\n \r\n\r\nAND opcode will logically AND the content of the two operands. Here the operands are at registers A and R0.\r\n\r\nAssume A= 10011101(9DH),<\/span>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\nANL A,R1\u00a0 which gives (A) \u2190 (A) <\/strong>\u2227 (R0)\r\n\r\nR0=11101110 (EEH)\r\n\r\nA=10001100 (8CH)\r\n

AND operation is done bitwise i.e if the first bit of A is 1 and first bit of R0 is 1 then the AND operation of A and R0 is 1. Hence the first bit is 1 which is stored as the result in Accumulator. Thus content of A register is 8CH.<\/span><\/p>\r\n

Clearing or resetting the content is done by CLR opcode.<\/span><\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n\u00a0 \u00a0 CLR A makes (A) = 0\r\n\r\nComplement is obtained through CPL.\r\n\r\n \r\n\r\nA=10001100\r\n\r\n \r\n\r\nCPL A ; (A) \u2190 (A\u2019) Which makes A=01100010<\/strong>\r\n\r\n \r\n\r\nFor swapping lower and upper nibble SWAP opcode is used, if A=10001100\r\n\r\n<\/div>\r\n
\r\n\r\n\u00a0 \u00a0SWAP A ;\u00a0\u00a0\u00a0\u00a0\u00a0 makes A=11011001=D9H, the LSB and MSB bits are swapped.\r\n\r\n \r\n\r\nInstruction set provides rotation of register content also (Figure 3 & 4).\r\n\r\n \r\n\r\nExamples for rotation:\r\n\r\n \r\n\r\nRotate Accumulator Left - RL A\r\n\r\n \r\n\r\nThe 8 bits of the accumulator are rotated left by one bit, and Bit D7 exits from the MSB and enters into LSB, D0\r\n\r\n \r\n\r\nif A = 1001110\r\n\r\n \r\n\r\nRL A\u00a0\u00a0\u00a0\u00a0\u00a0 makes A= 00111011(3EH),\r\n\r\n \r\n\r\n\"\"\r\n\r\n \r\n\r\nBoolean Operations - Bit-oriented Instructions :\r\n\r\n \r\n

Similar to logic instructions, bit-oriented instructions perform logic operations (Table.3). The difference is that these are performed upon single bits. All bit accesses are by direct addressing. Bit addresses 00H through 7FH are in the Lower 128, and bit addresses 80H through FFH are in SFR (special function register )space.<\/p>\r\n \r\n\r\nExamples\r\n\r\nANL C,bit ; Logical-AND for bit variables\r\n\r\n(C)\u00a0 <\/strong>\u2190 (C) <\/strong>\u2227 (bit)\r\n\r\nANL C,ACC.7 ;and carry with accum.bit 7\r\n\r\nMOV C,P1.0 ;load carry with input pin state\r\n\r\n<\/div>\r\n

\r\n\r\n\"\"\r\n\r\n \r\n

SETB instruction is used for setting the value of 1. The JC rel instruction is the jump carry instruction, rel refers to the relative address. JNC is jump on No carry to a particular address. JB instruction refers to jump on bit. JNB instruction is jump if bit is equal to zero. JBC instruction is jump if bit is equal to one and clears that bit.<\/p>\r\n \r\n\r\n1.1.3 Branch Instructions<\/em><\/strong>\r\n\r\n \r\n\r\nThere are two kinds of branch instructions:\r\n\r\n \r\n

Unconditional jump instructions: upon their execution a jump to a new location from where the program continues execution is performed.<\/p>\r\n \r\n

Conditional jump instructions: a jump to a new program location is executed only if a specified condition is met. Otherwise, the program normally proceeds with the next instruction. Table .4 gives the list of control jump instructions<\/p>\r\n \r\n\r\n \r\n\r\nIn unconditional branch instruction there are three types of jump instructions, namely :\r\n\r\n \r\n\r\nI.\u00a0 Short jump\r\n\r\n \r\n\r\nII. Absolute jump\r\n\r\n \r\n\r\nIII. Long jump.\r\n\r\n \r\n\r\n \r\n\r\nShort jump:\r\n\r\n \r\n

The SJMP instruction encodes the destination address as relative offset. The instruction is 2 bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of -128 to + 127 bytes relative to the instruction following the SJMP.<\/p>\r\n \r\n\r\nAbsolute jump :\r\n\r\n \r\n

The AJMP instruction encodes the destination address as an 11-bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by\u00a0another byte containing the low 8 bits of the destination address. When the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC. The high 5 bits stay the same.<\/span><\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\nHence the destination has to be within the same 2K block as the instruction following the AJMP.\r\n\r\n \r\n\r\n\"\"\r\n\r\n \r\n\r\nLong jump\r\n\r\n \r\n

The LJMP instruction encodes the destination address as a 16-bit constant. The instruction is 3 bytes long, consisting of the opcode and two address bytes. The destination address can be anywhere in the 64K Program Memory space.<\/p>\r\n \r\n\r\nCALL instructions are used for calling subroutines in 8051 controller.\r\n\r\n \r\n\r\nACALL addr11 (Absolute Call)\r\n\r\n \r\n

ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction.<\/p>\r\n \r\n\r\nLCALL addr16 (Long call)\r\n\r\n \r\n

LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two.The high -order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the<\/p>\r\n \r\n\r\nLCALL instruction.The subroutine may therefore begin anywhere in the full 64K byte program memory address space.\r\n\r\n \r\n\r\nConditional Jump :\r\n\r\n<\/div>\r\nDJNZ<byte>,<reladdr>(Decrement and Jump if Not Zero)\r\n\r\n \r\n

DJNZ 40H,LABEL_1; decrement content of address 40H if it is not zero, then go to LABEL_1 DJNZ R1,TOGGLE ; Decrement content of R1, if it is not zero then go to TOGGLE<\/p>\r\nCJNE <destbyte>,<src-byte>, rel (Compare and Jump if Not Equal)\r\n\r\n \r\n\r\nCJNE compares the magnitudes of the first two operands and branches if their values are not equal\r\n

The branch destination is computed by adding the signed relative -displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.<\/p>\r\n \r\n\r\nCJNE R7, # 60H, NOT_EQ\r\n\r\n \r\n

    \r\n \t
  1. Summary<\/strong><\/li>\r\n<\/ol>\r\n

    In this lecture Instruction set of 8051 is discussed. The Arithmetic and logical operations and the control transfer instructions are discussed with examples.<\/p>\r\n \r\n\r\nSupporting & Reference Materials<\/strong>\r\n

      \r\n \t
    1. The 8051 Microcontroller and Embedded Systems Using Assembly and C Second Edit Muhammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D.McKinlay.<\/li>\r\n \t
    2. www.mikroe.com\/chapters\/view\/66\/chapter-3-the-8051-instruction-set\/<\/li>\r\n<\/ol>\r\n
        \r\n \t
      1. References<\/strong><\/li>\r\n<\/ol>\r\n
          \r\n \t
        1. The 8051 Microcontroller and Embedded Systems Using Assembly and C Second Edition Muhammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D.McKinlay.<\/li>\r\n \t
        2. www.mikroe.com\/chapters\/view\/66\/chapter-3-the-8051-instruction-set\/<\/li>\r\n<\/ol>","rendered":"
          \n

           <\/p>\n

          In this lecture, Instruction set of 8051 microcontroller will be discussed in detail. Arithmetic and logical instructions, and control transfer instructions will be discussed with examples.<\/p>\n

           <\/p>\n

          1.Instruction set<\/strong><\/p>\n

           <\/p>\n

          The process of writing program for the microcontroller mainly consists of giving instructions (commands) in the specific order in which they should be executed in order to carry out a specific task. As digital circuit cannot \u201cunderstand\u201d what for example an instruction \u201cif the push button is pressed- turn the light on\u201d means, then a certain number of simpler and precisely defined orders that decoder can recognize must be used. All commands are known as INSTRUCTION SET. All microcontrollers compatible with the 8051 have a total of 255 instructions.<\/p>\n

           <\/p>\n

          In these 255 instructions, many instructions are considered to be \u201cdifferent\u201d, even though they perform the same operation, so there are only 111 truly different commands. For example: ADD A,R0, ADD A,R1, … ADD A,R7 are instructions that perform the same operation (addition of the accumulator and register). Since there are 8 such registers, each instruction is counted separately. Taking into account that all instructions perform only 53 operations (addition, subtraction, copy etc.) and most of them are rarely used in practice, there are actually 20-30 abbreviations to be learned, which is acceptable.<\/p>\n

           <\/p>\n

          1.1 Types of instructions<\/strong><\/p>\n

           <\/p>\n

          Depending on the operation that they perform, the instructions are divided into several groups:<\/p>\n

           <\/p>\n

          \u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Arithmetic Instructions<\/p>\n

          \u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Branch Instructions<\/p>\n

          \u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Data Transfer Instructions<\/p>\n

          \u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Logic Instructions and<\/p>\n

          \u25cf\u00a0\u00a0\u00a0\u00a0\u00a0 Bit-oriented Instructions.<\/p>\n

           <\/p>\n

          The first part of each instruction, called MNEMONIC refers to the operation an instruction performs (copy, addition, logic operation etc.). Mnemonics are abbreviations of the name of operation being executed. For example:<\/p>\n

           <\/p>\n

          ADD A, R0 – ADD mnemonic (A, R0- operands registers)<\/p>\n<\/div>\n

          \n

           <\/p>\n

          1.1.1 Arithmetic Instructions<\/em><\/strong><\/p>\n

           <\/p>\n

          Arithmetic instructions perform addition, subtraction, multiplication, division, increment and decrement operations. After execution, the result is stored in the first operand. For example: ADD<\/em> A,R1 – The result of addition (A+R1) will be stored in the accumulator.<\/em><\/p>\n

           <\/p>\n

          Table .1 Execution Table for Arithmetic instructions<\/p>\n

           <\/p>\n

          \"\"<\/p>\n

           <\/p>\n

          From Table.1 it is evident that always one of the operand is stored in accumulator. Addition is done through ADD and ADDC instruction. Addition with carry is needed when doing multiple addition. Subtraction is always done with borrow using SUBB instruction. Increment and decrement by one bit can be done with INC and DEC instructions. The DA A instruction is the decimal adjust used for BCD addition.<\/p>\n

           <\/p>\n

          The MUL AB instruction multiplies the Accumulator by the data in the B register and puts the 16-bit product into the concatenated B and Accumulator registers. The DIV AB instruction divides the Accumulator by the data in the B register and leaves the 8-bit quotient in the Accumulator, and the 8-bit remainder in the B register.<\/p>\n

           <\/p>\n

          Examples for addition and subtraction:<\/p>\n

           <\/p>\n

          ADD A,<src-byte><\/p>\n

          Assume A=09h and R0=07h<\/p>\n

          ADD A,R0 ; (A) \u2190 (A) + (R0), A=10h<\/strong><\/p>\n

          ADDC A,Rn ; (A) \u2190 (A) + (C) + (Rn)<\/strong><\/p>\n<\/div>\n

          \n

           <\/p>\n

          In the ADDC instruction of previous example if the carry bit is 1 then 10h+1 is 11h and that is stored in Accumulator.<\/p>\n

          SUBB A,<src-byte><\/p>\n

          Assume A=09h, R0=07h, carry flag=1<\/p>\n

          SUBB A,R0 ; (A) \u2190 (A) – (C) – (R0) , A=1<\/strong><\/p>\n

           <\/p>\n

          Examples for multiplication and division :<\/p>\n

           <\/p>\n

          Assume A=09h,B=02h<\/p>\n

           <\/p>\n

          \u2022\u00a0MUL AB ; (A)9 \u2190 (A) X (B)<\/strong><\/p>\n

          (B)2,\u00a0 A=12h,B=00h<\/p>\n

          Multiplying A and B gives 18 in decimal and in hexadecimal it is 12h. Here, LSB is stored in A register and MSB is stored in B register. There is no overflow in the above instruction, if there is overflow then those values are stored in B register.<\/p>\n

           <\/p>\n

          \u2022\u00a0DIV AB ; (A)9 \u2190 (A)\/(B)<\/strong><\/p>\n

           <\/p>\n

          (B)2 , A=04h,B=01h<\/p>\n

          Division of A and B gives quotient as 4 and remainder as 1. A holds the quotient and B holds the remainder.<\/p>\n

           <\/p>\n

          1.1.2. Logical Instruction<\/em><\/strong><\/p>\n

           <\/p>\n

          Logic instructions perform logic operations upon corresponding bits of two registers. After execution, the result is stored in the first operand. These instructions perform basic logic operations such as OR,AND,XOR ,complement and rotate operations.<\/p>\n<\/div>\n

          \n

          \"\"<\/p>\n

           <\/p>\n

          All logical instructions are listed in Table.2. Accumulator holds one of the operand always. ANL performs the logical AND operation. OR operation is performed through ORL instruction. XOR operation is done with XRL instruction. Reset to zero is done with CLR instruction. Complement is done with CLP. In assembly code rotation of data is also possible. Rotate left, rotate right can be done with accumulator content through RL and RR instructions. RLC and RRC will take care about rotating accumulator data with carry. SWAP will swap lower and upper nibbles of accumulator data. The execution time for all these instructions are listed in Table.2.<\/p>\n

           <\/p>\n

           <\/p>\n

          Example for Logical AND operation :<\/p>\n

           <\/p>\n

          AND opcode will logically AND the content of the two operands. Here the operands are at registers A and R0.<\/p>\n

          Assume A= 10011101(9DH),<\/span><\/p>\n<\/div>\n

          \n

           <\/p>\n

          ANL A,R1\u00a0 which gives (A) \u2190 (A) <\/strong>\u2227 (R0)<\/p>\n

          R0=11101110 (EEH)<\/p>\n

          A=10001100 (8CH)<\/p>\n

          AND operation is done bitwise i.e if the first bit of A is 1 and first bit of R0 is 1 then the AND operation of A and R0 is 1. Hence the first bit is 1 which is stored as the result in Accumulator. Thus content of A register is 8CH.<\/span><\/p>\n

          Clearing or resetting the content is done by CLR opcode.<\/span><\/p>\n<\/div>\n

          \n

          \u00a0 \u00a0 CLR A makes (A) = 0<\/p>\n

          Complement is obtained through CPL.<\/p>\n

           <\/p>\n

          A=10001100<\/p>\n

           <\/p>\n

          CPL A ; (A) \u2190 (A\u2019) Which makes A=01100010<\/strong><\/p>\n

           <\/p>\n

          For swapping lower and upper nibble SWAP opcode is used, if A=10001100<\/p>\n<\/div>\n

          \n

          \u00a0 \u00a0SWAP A ;\u00a0\u00a0\u00a0\u00a0\u00a0 makes A=11011001=D9H, the LSB and MSB bits are swapped.<\/p>\n

           <\/p>\n

          Instruction set provides rotation of register content also (Figure 3 & 4).<\/p>\n

           <\/p>\n

          Examples for rotation:<\/p>\n

           <\/p>\n

          Rotate Accumulator Left – RL A<\/p>\n

           <\/p>\n

          The 8 bits of the accumulator are rotated left by one bit, and Bit D7 exits from the MSB and enters into LSB, D0<\/p>\n

           <\/p>\n

          if A = 1001110<\/p>\n

           <\/p>\n

          RL A\u00a0\u00a0\u00a0\u00a0\u00a0 makes A= 00111011(3EH),<\/p>\n

           <\/p>\n

          \"\"<\/p>\n

           <\/p>\n

          Boolean Operations – Bit-oriented Instructions :<\/p>\n

           <\/p>\n

          Similar to logic instructions, bit-oriented instructions perform logic operations (Table.3). The difference is that these are performed upon single bits. All bit accesses are by direct addressing. Bit addresses 00H through 7FH are in the Lower 128, and bit addresses 80H through FFH are in SFR (special function register )space.<\/p>\n

           <\/p>\n

          Examples<\/p>\n

          ANL C,bit ; Logical-AND for bit variables<\/p>\n

          (C)\u00a0 <\/strong>\u2190 (C) <\/strong>\u2227 (bit)<\/p>\n

          ANL C,ACC.7 ;and carry with accum.bit 7<\/p>\n

          MOV C,P1.0 ;load carry with input pin state<\/p>\n<\/div>\n

          \n

          \"\"<\/p>\n

           <\/p>\n

          SETB instruction is used for setting the value of 1. The JC rel instruction is the jump carry instruction, rel refers to the relative address. JNC is jump on No carry to a particular address. JB instruction refers to jump on bit. JNB instruction is jump if bit is equal to zero. JBC instruction is jump if bit is equal to one and clears that bit.<\/p>\n

           <\/p>\n

          1.1.3 Branch Instructions<\/em><\/strong><\/p>\n

           <\/p>\n

          There are two kinds of branch instructions:<\/p>\n

           <\/p>\n

          Unconditional jump instructions: upon their execution a jump to a new location from where the program continues execution is performed.<\/p>\n

           <\/p>\n

          Conditional jump instructions: a jump to a new program location is executed only if a specified condition is met. Otherwise, the program normally proceeds with the next instruction. Table .4 gives the list of control jump instructions<\/p>\n

           <\/p>\n

           <\/p>\n

          In unconditional branch instruction there are three types of jump instructions, namely :<\/p>\n

           <\/p>\n

          I.\u00a0 Short jump<\/p>\n

           <\/p>\n

          II. Absolute jump<\/p>\n

           <\/p>\n

          III. Long jump.<\/p>\n

           <\/p>\n

           <\/p>\n

          Short jump:<\/p>\n

           <\/p>\n

          The SJMP instruction encodes the destination address as relative offset. The instruction is 2 bytes long, consisting of the opcode and the relative offset byte. The jump distance is limited to a range of -128 to + 127 bytes relative to the instruction following the SJMP.<\/p>\n

           <\/p>\n

          Absolute jump :<\/p>\n

           <\/p>\n

          The AJMP instruction encodes the destination address as an 11-bit constant. The instruction is 2 bytes long, consisting of the opcode, which itself contains 3 of the 11 address bits, followed by\u00a0another byte containing the low 8 bits of the destination address. When the instruction is executed, these 11 bits are simply substituted for the low 11 bits in the PC. The high 5 bits stay the same.<\/span><\/p>\n<\/div>\n

          \n

           <\/p>\n

          Hence the destination has to be within the same 2K block as the instruction following the AJMP.<\/p>\n

           <\/p>\n

          \"\"<\/p>\n

           <\/p>\n

          Long jump<\/p>\n

           <\/p>\n

          The LJMP instruction encodes the destination address as a 16-bit constant. The instruction is 3 bytes long, consisting of the opcode and two address bytes. The destination address can be anywhere in the 64K Program Memory space.<\/p>\n

           <\/p>\n

          CALL instructions are used for calling subroutines in 8051 controller.<\/p>\n

           <\/p>\n

          ACALL addr11 (Absolute Call)<\/p>\n

           <\/p>\n

          ACALL unconditionally calls a subroutine located at the indicated address. The instruction increments the PC twice to obtain the address of the following instruction, then pushes the 16-bit result onto the stack (low-order byte first) and increments the Stack Pointer twice. The destination address is obtained by successively concatenating the five high-order bits of the incremented PC, opcode bits 7 through 5, and the second byte of the instruction.<\/p>\n

           <\/p>\n

          LCALL addr16 (Long call)<\/p>\n

           <\/p>\n

          LCALL calls a subroutine located at the indicated address. The instruction adds three to the program counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack (low byte first), incrementing the Stack Pointer by two.The high -order and low-order bytes of the PC are then loaded, respectively, with the second and third bytes of the<\/p>\n

           <\/p>\n

          LCALL instruction.The subroutine may therefore begin anywhere in the full 64K byte program memory address space.<\/p>\n

           <\/p>\n

          Conditional Jump :<\/p>\n<\/div>\n

          DJNZ<byte>,<reladdr>(Decrement and Jump if Not Zero)<\/p>\n

           <\/p>\n

          DJNZ 40H,LABEL_1; decrement content of address 40H if it is not zero, then go to LABEL_1 DJNZ R1,TOGGLE ; Decrement content of R1, if it is not zero then go to TOGGLE<\/p>\n

          CJNE <destbyte>,<src-byte>, rel (Compare and Jump if Not Equal)<\/p>\n

           <\/p>\n

          CJNE compares the magnitudes of the first two operands and branches if their values are not equal<\/p>\n

          The branch destination is computed by adding the signed relative -displacement in the last instruction byte to the PC, after incrementing the PC to the start of the next instruction. The carry flag is set if the unsigned integer value of <dest-byte> is less than the unsigned integer value of <src-byte>; otherwise, the carry is cleared. Neither operand is affected.<\/p>\n

           <\/p>\n

          CJNE R7, # 60H, NOT_EQ<\/p>\n

           <\/p>\n

            \n
          1. Summary<\/strong><\/li>\n<\/ol>\n

            In this lecture Instruction set of 8051 is discussed. The Arithmetic and logical operations and the control transfer instructions are discussed with examples.<\/p>\n

             <\/p>\n

            Supporting & Reference Materials<\/strong><\/p>\n

              \n
            1. The 8051 Microcontroller and Embedded Systems Using Assembly and C Second Edit Muhammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D.McKinlay.<\/li>\n
            2. www.mikroe.com\/chapters\/view\/66\/chapter-3-the-8051-instruction-set\/<\/li>\n<\/ol>\n
                \n
              1. References<\/strong><\/li>\n<\/ol>\n
                  \n
                1. The 8051 Microcontroller and Embedded Systems Using Assembly and C Second Edition Muhammad Ali Mazidi, Janice Gillispie Mazidi and Rolin D.McKinlay.<\/li>\n
                2. www.mikroe.com\/chapters\/view\/66\/chapter-3-the-8051-instruction-set\/<\/li>\n<\/ol>\n","protected":false},"author":2,"menu_order":6,"template":"","meta":{"pb_show_title":"on","pb_short_title":"","pb_subtitle":"","pb_authors":[],"pb_section_license":""},"chapter-type":[],"contributor":[],"license":[],"class_list":["post-66","chapter","type-chapter","status-publish","hentry"],"part":3,"_links":{"self":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/66","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters"}],"about":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/types\/chapter"}],"author":[{"embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/users\/2"}],"version-history":[{"count":1,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/66\/revisions"}],"predecessor-version":[{"id":72,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/66\/revisions\/72"}],"part":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/parts\/3"}],"metadata":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/66\/metadata\/"}],"wp:attachment":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/media?parent=66"}],"wp:term":[{"taxonomy":"chapter-type","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapter-type?post=66"},{"taxonomy":"contributor","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/contributor?post=66"},{"taxonomy":"license","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/license?post=66"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}