{"id":230,"date":"2018-07-27T05:06:45","date_gmt":"2018-07-27T05:06:45","guid":{"rendered":"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/?post_type=chapter&#038;p=230"},"modified":"2018-07-27T06:09:41","modified_gmt":"2018-07-27T06:09:41","slug":"interrupt-programming-in-embedded-c","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/chapter\/interrupt-programming-in-embedded-c\/","title":{"rendered":"Interrupt Programming in Embedded C"},"content":{"raw":"<div>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">In this lecture embedded C program for interrupt handling will be discussed. Timer interrupt programming in Embedded C will be visited. Embedded C program for external hardware interrupt will be discussed in detail with examples.<\/p>\r\n&nbsp;\r\n\r\n<strong>1.\u00a0\u00a0 Interrupt Vs. Polling<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">External or internal event interrupts the microcontroller to inform it that a device needs its service. There are two ways to serving the device, they are interrupt and polling. Interrupt service begins when the device notifies the microcontroller by sending it an interrupt signal. After receiving an interrupt signal, the microcontroller stops whatever it is doing and serves the device. Program associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler. Polling happens while the microcontroller continuously monitors the status of a given device. When the condition is met, it performs the service. Next, it moves on to monitor the next device until everyone is serviced. Polling is not efficient, because it wastes much of the microcontroller\u2019s time by checking devices that do not need service. Interrupt can serve many devices, each device can get the service of microcontroller based on priority; but in polling, there is no priority, only on round robin they can get the attention of microcontroller. Microcontroller can also ignore a device request for service, because each interrupt is having an interrupt service routine (ISR), or interrupt handler. This is not possible in the polling method<\/p>\r\n&nbsp;\r\n\r\n<strong>1.1 Interrupt Service Routine(ISR):<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Each interrupt has an interrupt service routine (ISR), or interrupt handler. When an interrupt is called, the microcontroller runs the interrupt service routine. Every interrupt has a fixed location in memory that holds the address of the ISR. The group of memory locations that hold the addresses of ISRs is called interrupt vector table. Interrupt vector table for 8051 is shown in Table 1 below.<\/p>\r\n\r\n<\/div>\r\n<img class=\"size-full wp-image-233 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128.png\" alt=\"\" width=\"600\" height=\"241\" \/>\r\n<div>\r\n\r\n<strong>1.2 Six interrupts in the 8051.<\/strong>\r\n\r\n&nbsp;\r\n\r\nSix interrupts in the 8051 are allocated as follows:\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf Reset \u2013 When the reset pin is activated, the 8051 jumps into memory location 0000. This is the power-up reset.<\/p>\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf Two interrupts are set aside for the timers:One for timer 0 and one for timer 1.<\/p>\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf Two interrupts are set aside for hardware external interrupts. Pin numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware interrupts INT0 (or EX1), and INT1 (or EX2).<\/p>\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf Serial communication has a single interrupt that belongs to both receive and transmit. The interrupt vector table location 0023H belongs to this interrupt.<\/p>\r\n&nbsp;\r\n\r\n<strong>1.3 Steps in enabling the interrupt<\/strong>\r\n\r\n&nbsp;\r\n\r\nThe following are the steps to enable the interrupt in 8051:\r\n\r\n&nbsp;\r\n\r\n1.\u00a0\u00a0\u00a0 Bit D7 of the IE register (EA) must be set to high to allow the rest of the register to take effect.\r\n\r\n&nbsp;\r\n\r\n2.\u00a0\u00a0\u00a0 If EA=1 enable all interrupts, EA=0 disable all interrupts even if the associated bit in the IE register is high.\r\n\r\n&nbsp;\r\n\r\nThe figure 1 shown below gives the details about IE (Interrupt Enable) registers.\r\n\r\n&nbsp;\r\n\r\n<img class=\"size-full wp-image-235 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129.png\" alt=\"\" width=\"529\" height=\"276\" \/>\r\n\r\n<strong>1.4 8051 C interrupt numbers<\/strong>\r\n\r\n&nbsp;\r\n\r\nThe 8051 C compilers have extensive support for 8051 interrupt with two features. They are\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf\u00a0\u00a0\u00a0\u00a0 Assign a unique number to each of the 8051 interrupts. It is shown in Table 2 shown below.<\/p>\r\n<p style=\"text-align: justify\">\u25cf\u00a0\u00a0\u00a0\u00a0 It can also assign a register bank to ISR. This avoids code overhead due to push and pop operation of the R0-R7 registers.<\/p>\r\n\r\n<\/div>\r\n<div>\r\n\r\n<img class=\"size-full wp-image-236 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130.png\" alt=\"\" width=\"454\" height=\"255\" \/>\r\n\r\n&nbsp;\r\n\r\n<strong>1.5 Programmable Timer Interrupt<\/strong>\r\n\r\n&nbsp;\r\n\r\nThe timer flag (TF) is raised when the timer rolls over.\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf In polling mode, we have to wait until the TF is raised. The microcontroller is tied down while waiting for TF to be raised, and cannot do anything else.<\/p>\r\n&nbsp;\r\n<p style=\"text-align: justify\">\u25cf If the timer interrupt in the IE register is enabled, whenever the timer rolls over, the Timer Flag is raised. After that the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR. In this way, the microcontroller can do other work until it is notified that the timer has rolled over.<\/p>\r\n&nbsp;\r\n<p style=\"text-align: justify\">The figure 2 shown below gives the details about TF interrupt. If the timer interrupt is enabled, whenever TF=1, the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR.<\/p>\r\n&nbsp;\r\n\r\n<img class=\"size-full wp-image-237 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131.png\" alt=\"\" width=\"577\" height=\"122\" \/>\r\n\r\nThe Example 1 gives details about generating a square wave using Timer 0 assuming that XTAL value is 11.0592 MHz\r\n\r\n&nbsp;\r\n\r\n<strong>Example 1<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0, while simultaneously creating a square wave of 200 \u03bcs period on pin P2.5. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz<\/p>\r\n&nbsp;\r\n\r\n<strong>Solution<\/strong><strong>:<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">We will use timer 0 in mode 2 (auto-reload). One half of the period is100 \u03bcs. 100\/1.085 \u03bcs = 92, and TH0 = 256 - 92 = 164 or A4H.<\/p>\r\n&nbsp;\r\n\r\n#include &lt;reg51.h&gt;\r\n\r\nsbit SW =P1^7;\r\n\r\n<\/div>\r\n<span style=\"text-align: initial;font-size: 1em\">\u00a0 sbit IND =P1^0;<\/span>\r\n<div>\r\n\r\nsbit WAVE =P2^5;\r\n\r\n&nbsp;\r\n\r\nvoid timer0(void) interrupt 1\r\n\r\n&nbsp;\r\n\r\n{\r\n\r\nWAVE=~WAVE; \/\/toggle pin\r\n\r\n}\r\n\r\nvoid main()\r\n\r\n{\r\n\r\nSW=1; \/\/make switch input\r\n\r\nTMOD=0x02;\r\n\r\nTH0=0xA4; \/\/TH0=-92\r\n\r\nIE=0x82; \/\/enable interrupt for timer 0\r\n\r\nwhile (1)\r\n\r\n{\r\n\r\nIND=SW; \/\/send switch to LED\r\n\r\n}\r\n\r\n}\r\n\r\n&nbsp;\r\n\r\n<strong>1.6 Programming the Serial Communication Interrupt<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">There is only one interrupt for serial communication. It is used to both send and receive the data. If the interrupt bit in the IE register (IE.4) is enabled, when RI (Received interrupt) or TI (transfer interrupt) is raised, the 8051 gets interrupted and jumps to memory location 0023H to execute the ISR. In ISR, the programmer has to examine the TI and RI flags to see which one has caused the interrupt and take action accordingly. Serial interrupt mainly used for receiving and not for sending the data. The following figure 3 es Single interrupt for both TI and RI flag.<\/p>\r\n&nbsp;\r\n\r\n<img class=\"size-full wp-image-238 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132.png\" alt=\"\" width=\"684\" height=\"153\" \/>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Example 2 described below is used for creating a square wave of 200 us period on pin P2.5 and sending letter \u2018A\u2019 to the serial port. It uses Timer0 to create the square wave.<\/p>\r\n&nbsp;\r\n\r\n<strong>Example 2:<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0, while simultaneously (a) creating a square wave of 200 us period on pin P2.5, and (b) sending letter \u2018A\u2019 to the serial port. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz. Use the 9600 baud rate.<\/p>\r\n&nbsp;\r\n\r\n<strong>Solution:<\/strong>\r\n\r\n<\/div>\r\n<strong>\u00a0<img class=\"size-full wp-image-239 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133.png\" alt=\"\" width=\"519\" height=\"535\" \/><\/strong>\r\n<div>\r\n\r\n<strong>2. Programming the External hardware interrupt<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Two external hardware interrupts are available in 8051.They are Level triggered and Edge triggered interrupt. The interrupt vector table locations 0003H and 0013H are set aside for INT0 and INT1.<\/p>\r\n&nbsp;\r\n\r\n<strong>Level Triggered Interrupt:<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">The level-triggered or level-activated interrupt is the default mode upon reset of the 8051. INT0 and INT1 pins are normally high in the level trigger mode, while the low-level signal on INT0 or INT1 triggers the interrupt. Once the interrupt occurs, the microcontroller stops whatever it is doing and jumps to the interrupt vector table to service that interrupt. The low-level interrupt signal is to be removed before the execution of the last instruction of the ISR, RETI. If low level signal is not removed it results in another interrupt being generated.<\/p>\r\n&nbsp;\r\n\r\n<strong>Edge Triggered Interrupt:<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">To make INT0 and INT1 edge triggered interrupts, we must program the bits of the TCON register. The details of TCON register is given in Table 3.<\/p>\r\n\r\n<\/div>\r\n<div>\r\n\r\n<img class=\"size-full wp-image-240 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134.png\" alt=\"\" width=\"599\" height=\"403\" \/>\r\n\r\n&nbsp;\r\n\r\n<strong>2.1 Sampling the edge-triggered interrupt<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">The external source must be held high for at least one machine cycle, and then held low for at least one machine cycle. The falling edge of pins INT0 and INT1 are latched by the 8051 and are held by the TCON.1 and TCON.3 bits of TCON register. These function as interrupt-in-service flags. It indicates that the interrupt is being serviced now. On this INTn pin, no new interrupt will be responded to until this service is finished. When the ISRs are finished, TCON.1 and TCON.3 are cleared. The interrupt is finished and the 8051 is ready to respond to another interrupt on that pin. During the time that the interrupt service routine is being executed, the INTn pin is ignored, no matter how many times it makes a high-to-low transition. RETI clears the corresponding bit in TCON register (TCON.1 or TCON.3). There is no need for instruction CLR TCON.1 before RETI in the ISR associated with INT0.<\/p>\r\n&nbsp;\r\n<p style=\"text-align: justify\">Example 3 described below shows a C program to Light all LEDS connected to Port 0 if the switch is pressed and display \u201cy\u201d at port2.<\/p>\r\n&nbsp;\r\n\r\n<strong>Example 3:<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">A switch is connected to pin P3.2. When switch is pressed the corresponding line goes low. Write a C program to Light all LEDS connected to Port 0 if the switch is pressed. Display \u201cy\u201d at port2.<\/p>\r\n&nbsp;\r\n\r\n<strong>Solution:<\/strong>\r\n\r\n&nbsp;\r\n\r\n#\u00a0 include &lt;reg51.h&gt; Sbit switch = P3^2;\r\n\r\nvoid extint0() \/\/ interrupt 0\r\n\r\n<\/div>\r\n<div>\r\n\r\n{\r\n\r\nP0=0xFF;\r\n\r\n}\r\n\r\n&nbsp;\r\n\r\nvoid main()\r\n\r\n{\r\n\r\nSwitch=1;\r\n\r\nIE=0x81;\r\n\r\nWhile(1)\r\n\r\n{\r\n\r\nP2=\u201cy\u201d;\r\n\r\n}\r\n\r\n}\r\n\r\n&nbsp;\r\n\r\n<strong>2.2 Interrupt Flag Bits for 8051<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">The TCON register holds four of the interrupt flags in the 8051. The interrupt flag bits for 8051 are shown in Table 4. The SCON register has the RI and TI flags.<\/p>\r\n&nbsp;\r\n\r\n<img class=\"size-full wp-image-241 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135.png\" alt=\"\" width=\"431\" height=\"230\" \/>\r\n\r\nExample 4 shown below gives the C program to receive data serially and send it to P0.\r\n\r\n&nbsp;\r\n\r\n<strong>Example 4<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Write a C program using interrupts to do the following: (a) Receive data serially and send it to P0 (b) Read port P1, transmit data serially, and give a copy to P2 (c) Make timer 0 generate a square wave of 5 kHz frequency on P0.1. Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.<\/p>\r\n&nbsp;\r\n\r\n<strong>Solution:<\/strong>\r\n\r\n&nbsp;\r\n\r\nvoid main()\r\n\r\n{\r\n\r\nunsigned char x;\r\n\r\nP1=0xFF; \/\/make P1 an input\r\n\r\nTMOD=0x22;\r\n\r\nTH1=0xF6; \/\/4800 baud rate\r\n\r\nSCON=0x50;\r\n\r\nTH0=0xA4; \/\/5 kHz has T=200us\r\n\r\n<\/div>\r\n&nbsp;\r\n<div>\r\n\r\nIE=0x92; \/\/enable interrupts\r\n\r\nTR1=1; \/\/start timer 1\r\n\r\nTR0=1; \/\/start timer 0\r\n\r\nwhile (1)\r\n\r\n{\r\n\r\nx=P1; \/\/read value from pins\r\n\r\nSBUF=x; \/\/put value in buffer\r\n\r\nP2=x; \/\/write value to pins\r\n\r\n}\r\n\r\n}\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">Example 5 gives the details about how to write an Embedded C program to generate 10 KHz frequency wave and use timer 1 as an event counter to count up to 1-Hz pulse.<\/p>\r\n&nbsp;\r\n\r\n<strong>Example 5<\/strong>\r\n\r\n&nbsp;\r\n\r\nWrite a C program using interrupts to do the following:\r\n\r\n(a) Generate a 10 KHz frequency on P2.1 using T0 8-bit auto-reload\r\n\r\n&nbsp;\r\n\r\n(b)\u00a0 Use timer 1 as an event counter to count up a 1-Hz pulse and display it on P0. The pulse is connected to EX1. Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.\r\n\r\n<strong>Solution:<\/strong>\r\n\r\n&nbsp;\r\n\r\n#include &lt;reg51.h&gt;\r\n\r\nsbit WAVE =P2^1;\r\n\r\nUnsigned char cnt;\r\n\r\nvoid timer0() interrupt 1\r\n\r\n{\r\n\r\nWAVE=~WAVE; \/\/toggle pin\r\n\r\n}\r\n\r\nvoid timer1() interrupt 3\r\n\r\n{\r\n\r\ncnt++; \/\/increment counter\r\n\r\nP0=cnt; \/\/display value on pins\r\n\r\n}\r\n\r\nvoid main()\r\n\r\n{\r\n\r\ncnt=0; \/\/set counter to 0\r\n\r\nTMOD=0x42;\r\n\r\nTH0=0x-46; \/\/10 KHz\r\n\r\nIE=0x86; \/\/enable interrupts\r\n\r\nTR0=1; \/\/start timer 0\r\n\r\nwhile (1); \/\/wait until interrupted\r\n\r\n}\r\n\r\n&nbsp;\r\n\r\n<strong>3. Summary<\/strong>\r\n\r\n&nbsp;\r\n<p style=\"text-align: justify\">In this lecture interrupt handling in 8051 has been discussed. Timer interrupt programming in 8051 is discussed with examples. External interrupt programming in embedded C is discussed in detail.<\/p>\r\n\r\n<\/div>\r\n<ol start=\"4\">\r\n \t<li><strong>References<\/strong><\/li>\r\n<\/ol>\r\n<p style=\"text-align: justify\"><strong>\u00a01.\u00a0<\/strong><span style=\"font-size: 1em\">The 8051 Microcontroller and Embedded Systems Using Assembly and C Second Edition Muhammad Ali Mazidi, Janice Gillispie, Mazidi and Rolin D. McKinlay.<\/span><\/p>","rendered":"<div>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">In this lecture embedded C program for interrupt handling will be discussed. Timer interrupt programming in Embedded C will be visited. Embedded C program for external hardware interrupt will be discussed in detail with examples.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>1.\u00a0\u00a0 Interrupt Vs. Polling<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">External or internal event interrupts the microcontroller to inform it that a device needs its service. There are two ways to serving the device, they are interrupt and polling. Interrupt service begins when the device notifies the microcontroller by sending it an interrupt signal. After receiving an interrupt signal, the microcontroller stops whatever it is doing and serves the device. Program associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler. Polling happens while the microcontroller continuously monitors the status of a given device. When the condition is met, it performs the service. Next, it moves on to monitor the next device until everyone is serviced. Polling is not efficient, because it wastes much of the microcontroller\u2019s time by checking devices that do not need service. Interrupt can serve many devices, each device can get the service of microcontroller based on priority; but in polling, there is no priority, only on round robin they can get the attention of microcontroller. Microcontroller can also ignore a device request for service, because each interrupt is having an interrupt service routine (ISR), or interrupt handler. This is not possible in the polling method<\/p>\n<p>&nbsp;<\/p>\n<p><strong>1.1 Interrupt Service Routine(ISR):<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Each interrupt has an interrupt service routine (ISR), or interrupt handler. When an interrupt is called, the microcontroller runs the interrupt service routine. Every interrupt has a fixed location in memory that holds the address of the ISR. The group of memory locations that hold the addresses of ISRs is called interrupt vector table. Interrupt vector table for 8051 is shown in Table 1 below.<\/p>\n<\/div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-233 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128.png\" alt=\"\" width=\"600\" height=\"241\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128.png 600w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128-300x121.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128-65x26.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128-225x90.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-128-350x141.png 350w\" sizes=\"auto, (max-width: 600px) 100vw, 600px\" \/><\/p>\n<div>\n<p><strong>1.2 Six interrupts in the 8051.<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>Six interrupts in the 8051 are allocated as follows:<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf Reset \u2013 When the reset pin is activated, the 8051 jumps into memory location 0000. This is the power-up reset.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf Two interrupts are set aside for the timers:One for timer 0 and one for timer 1.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf Two interrupts are set aside for hardware external interrupts. Pin numbers 12 (P3.2) and 13 (P3.3) in port 3 are for the external hardware interrupts INT0 (or EX1), and INT1 (or EX2).<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf Serial communication has a single interrupt that belongs to both receive and transmit. The interrupt vector table location 0023H belongs to this interrupt.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>1.3 Steps in enabling the interrupt<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>The following are the steps to enable the interrupt in 8051:<\/p>\n<p>&nbsp;<\/p>\n<p>1.\u00a0\u00a0\u00a0 Bit D7 of the IE register (EA) must be set to high to allow the rest of the register to take effect.<\/p>\n<p>&nbsp;<\/p>\n<p>2.\u00a0\u00a0\u00a0 If EA=1 enable all interrupts, EA=0 disable all interrupts even if the associated bit in the IE register is high.<\/p>\n<p>&nbsp;<\/p>\n<p>The figure 1 shown below gives the details about IE (Interrupt Enable) registers.<\/p>\n<p>&nbsp;<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-235 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129.png\" alt=\"\" width=\"529\" height=\"276\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129.png 529w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129-300x157.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129-65x34.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129-225x117.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-129-350x183.png 350w\" sizes=\"auto, (max-width: 529px) 100vw, 529px\" \/><\/p>\n<p><strong>1.4 8051 C interrupt numbers<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>The 8051 C compilers have extensive support for 8051 interrupt with two features. They are<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf\u00a0\u00a0\u00a0\u00a0 Assign a unique number to each of the 8051 interrupts. It is shown in Table 2 shown below.<\/p>\n<p style=\"text-align: justify\">\u25cf\u00a0\u00a0\u00a0\u00a0 It can also assign a register bank to ISR. This avoids code overhead due to push and pop operation of the R0-R7 registers.<\/p>\n<\/div>\n<div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-236 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130.png\" alt=\"\" width=\"454\" height=\"255\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130.png 454w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130-300x169.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130-65x37.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130-225x126.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-130-350x197.png 350w\" sizes=\"auto, (max-width: 454px) 100vw, 454px\" \/><\/p>\n<p>&nbsp;<\/p>\n<p><strong>1.5 Programmable Timer Interrupt<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>The timer flag (TF) is raised when the timer rolls over.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf In polling mode, we have to wait until the TF is raised. The microcontroller is tied down while waiting for TF to be raised, and cannot do anything else.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">\u25cf If the timer interrupt in the IE register is enabled, whenever the timer rolls over, the Timer Flag is raised. After that the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR. In this way, the microcontroller can do other work until it is notified that the timer has rolled over.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">The figure 2 shown below gives the details about TF interrupt. If the timer interrupt is enabled, whenever TF=1, the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR.<\/p>\n<p>&nbsp;<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-237 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131.png\" alt=\"\" width=\"577\" height=\"122\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131.png 577w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131-300x63.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131-65x14.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131-225x48.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-131-350x74.png 350w\" sizes=\"auto, (max-width: 577px) 100vw, 577px\" \/><\/p>\n<p>The Example 1 gives details about generating a square wave using Timer 0 assuming that XTAL value is 11.0592 MHz<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Example 1<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0, while simultaneously creating a square wave of 200 \u03bcs period on pin P2.5. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Solution<\/strong><strong>:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">We will use timer 0 in mode 2 (auto-reload). One half of the period is100 \u03bcs. 100\/1.085 \u03bcs = 92, and TH0 = 256 &#8211; 92 = 164 or A4H.<\/p>\n<p>&nbsp;<\/p>\n<p>#include &lt;reg51.h&gt;<\/p>\n<p>sbit SW =P1^7;<\/p>\n<\/div>\n<p><span style=\"text-align: initial;font-size: 1em\">\u00a0 sbit IND =P1^0;<\/span><\/p>\n<div>\n<p>sbit WAVE =P2^5;<\/p>\n<p>&nbsp;<\/p>\n<p>void timer0(void) interrupt 1<\/p>\n<p>&nbsp;<\/p>\n<p>{<\/p>\n<p>WAVE=~WAVE; \/\/toggle pin<\/p>\n<p>}<\/p>\n<p>void main()<\/p>\n<p>{<\/p>\n<p>SW=1; \/\/make switch input<\/p>\n<p>TMOD=0x02;<\/p>\n<p>TH0=0xA4; \/\/TH0=-92<\/p>\n<p>IE=0x82; \/\/enable interrupt for timer 0<\/p>\n<p>while (1)<\/p>\n<p>{<\/p>\n<p>IND=SW; \/\/send switch to LED<\/p>\n<p>}<\/p>\n<p>}<\/p>\n<p>&nbsp;<\/p>\n<p><strong>1.6 Programming the Serial Communication Interrupt<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">There is only one interrupt for serial communication. It is used to both send and receive the data. If the interrupt bit in the IE register (IE.4) is enabled, when RI (Received interrupt) or TI (transfer interrupt) is raised, the 8051 gets interrupted and jumps to memory location 0023H to execute the ISR. In ISR, the programmer has to examine the TI and RI flags to see which one has caused the interrupt and take action accordingly. Serial interrupt mainly used for receiving and not for sending the data. The following figure 3 es Single interrupt for both TI and RI flag.<\/p>\n<p>&nbsp;<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-238 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132.png\" alt=\"\" width=\"684\" height=\"153\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132.png 684w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132-300x67.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132-65x15.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132-225x50.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-132-350x78.png 350w\" sizes=\"auto, (max-width: 684px) 100vw, 684px\" \/><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Example 2 described below is used for creating a square wave of 200 us period on pin P2.5 and sending letter \u2018A\u2019 to the serial port. It uses Timer0 to create the square wave.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Example 2:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Write a C program that continuously gets a single bit of data from P1.7 and sends it to P1.0, while simultaneously (a) creating a square wave of 200 us period on pin P2.5, and (b) sending letter \u2018A\u2019 to the serial port. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz. Use the 9600 baud rate.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Solution:<\/strong><\/p>\n<\/div>\n<p><strong>\u00a0<img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-239 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133.png\" alt=\"\" width=\"519\" height=\"535\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133.png 519w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133-291x300.png 291w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133-65x67.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133-225x232.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-133-350x361.png 350w\" sizes=\"auto, (max-width: 519px) 100vw, 519px\" \/><\/strong><\/p>\n<div>\n<p><strong>2. Programming the External hardware interrupt<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Two external hardware interrupts are available in 8051.They are Level triggered and Edge triggered interrupt. The interrupt vector table locations 0003H and 0013H are set aside for INT0 and INT1.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Level Triggered Interrupt:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">The level-triggered or level-activated interrupt is the default mode upon reset of the 8051. INT0 and INT1 pins are normally high in the level trigger mode, while the low-level signal on INT0 or INT1 triggers the interrupt. Once the interrupt occurs, the microcontroller stops whatever it is doing and jumps to the interrupt vector table to service that interrupt. The low-level interrupt signal is to be removed before the execution of the last instruction of the ISR, RETI. If low level signal is not removed it results in another interrupt being generated.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Edge Triggered Interrupt:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">To make INT0 and INT1 edge triggered interrupts, we must program the bits of the TCON register. The details of TCON register is given in Table 3.<\/p>\n<\/div>\n<div>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-240 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134.png\" alt=\"\" width=\"599\" height=\"403\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134.png 599w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134-300x202.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134-65x44.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134-225x151.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-134-350x235.png 350w\" sizes=\"auto, (max-width: 599px) 100vw, 599px\" \/><\/p>\n<p>&nbsp;<\/p>\n<p><strong>2.1 Sampling the edge-triggered interrupt<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">The external source must be held high for at least one machine cycle, and then held low for at least one machine cycle. The falling edge of pins INT0 and INT1 are latched by the 8051 and are held by the TCON.1 and TCON.3 bits of TCON register. These function as interrupt-in-service flags. It indicates that the interrupt is being serviced now. On this INTn pin, no new interrupt will be responded to until this service is finished. When the ISRs are finished, TCON.1 and TCON.3 are cleared. The interrupt is finished and the 8051 is ready to respond to another interrupt on that pin. During the time that the interrupt service routine is being executed, the INTn pin is ignored, no matter how many times it makes a high-to-low transition. RETI clears the corresponding bit in TCON register (TCON.1 or TCON.3). There is no need for instruction CLR TCON.1 before RETI in the ISR associated with INT0.<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Example 3 described below shows a C program to Light all LEDS connected to Port 0 if the switch is pressed and display \u201cy\u201d at port2.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Example 3:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">A switch is connected to pin P3.2. When switch is pressed the corresponding line goes low. Write a C program to Light all LEDS connected to Port 0 if the switch is pressed. Display \u201cy\u201d at port2.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Solution:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>#\u00a0 include &lt;reg51.h&gt; Sbit switch = P3^2;<\/p>\n<p>void extint0() \/\/ interrupt 0<\/p>\n<\/div>\n<div>\n<p>{<\/p>\n<p>P0=0xFF;<\/p>\n<p>}<\/p>\n<p>&nbsp;<\/p>\n<p>void main()<\/p>\n<p>{<\/p>\n<p>Switch=1;<\/p>\n<p>IE=0x81;<\/p>\n<p>While(1)<\/p>\n<p>{<\/p>\n<p>P2=\u201cy\u201d;<\/p>\n<p>}<\/p>\n<p>}<\/p>\n<p>&nbsp;<\/p>\n<p><strong>2.2 Interrupt Flag Bits for 8051<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">The TCON register holds four of the interrupt flags in the 8051. The interrupt flag bits for 8051 are shown in Table 4. The SCON register has the RI and TI flags.<\/p>\n<p>&nbsp;<\/p>\n<p><img loading=\"lazy\" decoding=\"async\" class=\"size-full wp-image-241 aligncenter\" src=\"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135.png\" alt=\"\" width=\"431\" height=\"230\" srcset=\"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135.png 431w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135-300x160.png 300w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135-65x35.png 65w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135-225x120.png 225w, https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-content\/uploads\/sites\/62\/2018\/07\/2-135-350x187.png 350w\" sizes=\"auto, (max-width: 431px) 100vw, 431px\" \/><\/p>\n<p>Example 4 shown below gives the C program to receive data serially and send it to P0.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Example 4<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Write a C program using interrupts to do the following: (a) Receive data serially and send it to P0 (b) Read port P1, transmit data serially, and give a copy to P2 (c) Make timer 0 generate a square wave of 5 kHz frequency on P0.1. Assume that XTAL = 11.0592 MHz. Set the baud rate at 4800.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Solution:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>void main()<\/p>\n<p>{<\/p>\n<p>unsigned char x;<\/p>\n<p>P1=0xFF; \/\/make P1 an input<\/p>\n<p>TMOD=0x22;<\/p>\n<p>TH1=0xF6; \/\/4800 baud rate<\/p>\n<p>SCON=0x50;<\/p>\n<p>TH0=0xA4; \/\/5 kHz has T=200us<\/p>\n<\/div>\n<p>&nbsp;<\/p>\n<div>\n<p>IE=0x92; \/\/enable interrupts<\/p>\n<p>TR1=1; \/\/start timer 1<\/p>\n<p>TR0=1; \/\/start timer 0<\/p>\n<p>while (1)<\/p>\n<p>{<\/p>\n<p>x=P1; \/\/read value from pins<\/p>\n<p>SBUF=x; \/\/put value in buffer<\/p>\n<p>P2=x; \/\/write value to pins<\/p>\n<p>}<\/p>\n<p>}<\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">Example 5 gives the details about how to write an Embedded C program to generate 10 KHz frequency wave and use timer 1 as an event counter to count up to 1-Hz pulse.<\/p>\n<p>&nbsp;<\/p>\n<p><strong>Example 5<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>Write a C program using interrupts to do the following:<\/p>\n<p>(a) Generate a 10 KHz frequency on P2.1 using T0 8-bit auto-reload<\/p>\n<p>&nbsp;<\/p>\n<p>(b)\u00a0 Use timer 1 as an event counter to count up a 1-Hz pulse and display it on P0. The pulse is connected to EX1. Assume that XTAL = 11.0592 MHz. Set the baud rate at 9600.<\/p>\n<p><strong>Solution:<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p>#include &lt;reg51.h&gt;<\/p>\n<p>sbit WAVE =P2^1;<\/p>\n<p>Unsigned char cnt;<\/p>\n<p>void timer0() interrupt 1<\/p>\n<p>{<\/p>\n<p>WAVE=~WAVE; \/\/toggle pin<\/p>\n<p>}<\/p>\n<p>void timer1() interrupt 3<\/p>\n<p>{<\/p>\n<p>cnt++; \/\/increment counter<\/p>\n<p>P0=cnt; \/\/display value on pins<\/p>\n<p>}<\/p>\n<p>void main()<\/p>\n<p>{<\/p>\n<p>cnt=0; \/\/set counter to 0<\/p>\n<p>TMOD=0x42;<\/p>\n<p>TH0=0x-46; \/\/10 KHz<\/p>\n<p>IE=0x86; \/\/enable interrupts<\/p>\n<p>TR0=1; \/\/start timer 0<\/p>\n<p>while (1); \/\/wait until interrupted<\/p>\n<p>}<\/p>\n<p>&nbsp;<\/p>\n<p><strong>3. Summary<\/strong><\/p>\n<p>&nbsp;<\/p>\n<p style=\"text-align: justify\">In this lecture interrupt handling in 8051 has been discussed. Timer interrupt programming in 8051 is discussed with examples. External interrupt programming in embedded C is discussed in detail.<\/p>\n<\/div>\n<ol start=\"4\">\n<li><strong>References<\/strong><\/li>\n<\/ol>\n<p style=\"text-align: justify\"><strong>\u00a01.\u00a0<\/strong><span style=\"font-size: 1em\">The 8051 Microcontroller and Embedded Systems Using Assembly and C Second Edition Muhammad Ali Mazidi, Janice Gillispie, Mazidi and Rolin D. McKinlay.<\/span><\/p>\n","protected":false},"author":2,"menu_order":19,"template":"","meta":{"pb_show_title":"on","pb_short_title":"","pb_subtitle":"","pb_authors":["dr-k-vani"],"pb_section_license":""},"chapter-type":[],"contributor":[58],"license":[],"class_list":["post-230","chapter","type-chapter","status-publish","hentry","contributor-dr-k-vani"],"part":3,"_links":{"self":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/230","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters"}],"about":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/types\/chapter"}],"author":[{"embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/users\/2"}],"version-history":[{"count":4,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/230\/revisions"}],"predecessor-version":[{"id":242,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/230\/revisions\/242"}],"part":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/parts\/3"}],"metadata":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/230\/metadata\/"}],"wp:attachment":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/media?parent=230"}],"wp:term":[{"taxonomy":"chapter-type","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapter-type?post=230"},{"taxonomy":"contributor","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/contributor?post=230"},{"taxonomy":"license","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/license?post=230"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}