{"id":161,"date":"2018-07-26T11:37:16","date_gmt":"2018-07-26T11:37:16","guid":{"rendered":"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/?post_type=chapter&p=161"},"modified":"2018-08-13T05:32:08","modified_gmt":"2018-08-13T05:32:08","slug":"memory-system","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/chapter\/memory-system\/","title":{"rendered":"Memory System"},"content":{"raw":" \r\n

In this lecture, the semiconductor memory will be discussed in detail. Memory address decoding and the interfacing of 8051 will also be discussed.<\/p>\r\n \r\n\r\n1.<\/strong>Semiconductor Memory<\/strong>\r\n\r\n \r\n\r\n1.1 Memory Capacity:<\/strong>\r\n\r\n \r\n

The number of bits that a semiconductor memory chip can store is called chip capacity. It can be in units of Kbits (kilobits), Mbits (megabits), and so on.<\/p>\r\n \r\n

This must be distinguished from the storage capacity of computer systems.<\/p>\r\n \r\n

While the memory capacity of a memory IC chip is always given in bits, the memory capacity of a computer system is given in bytes. If a 16M memory chip is present, then 16 megabits is stored in the semiconductor memory. If a computer comes with 16M memory, 16 megabytes can be stored which means that 16 words are stored, each with the capacity of 8 bits.<\/p>\r\n \r\n\r\n1.2 Memory Organization<\/strong>\r\n\r\n \r\n

Memory chips are organized into a number of locations within the IC. Each location can hold 1 bit, 4 bits, 8 bits, or even 16 bits, depending on how it is designed internally. The number of locations within a memory IC depends on the address pins. The number of bits that each location can hold is always equal to the number of data pins. In general, if x is the number of address lines in a memory chip, it contains 2x locations. Dynamic RAMs (DRAMs) are exceptions to this as indicated in a later section (1.9.2). Each location contains y bits, where y is the number of data pins on the chip. The entire chip will contain 2x \u00d7 y bits.<\/p>\r\n \r\n\r\n\"\"\r\n

\r\n\r\n \r\n

Figure 1.1 shows the memory capacity where x is the number of address pins and 2x the corresponding memory capacity.<\/p>\r\n \r\n\r\n1.2.1 Example for memory organization<\/em><\/strong>\r\n\r\n \r\n

A 512K memory chip has 8 pins for data. Find: (a) The organization, and (b) the number of address pins for this memory chip.<\/p>\r\n \r\n\r\nSolution:<\/strong>\r\n\r\n \r\n

(a)\u00a0 A memory chip with 8 data pins means that each location within the chip can hold 8 bits of data. To find the number of locations within this memory chip, divide the capacity by the number of data pins. 512K\/8 = 64K; therefore, the organization for this memory chip is 64K \u00d7 8.<\/p>\r\n \r\n

(b) The chip has 16 address lines since 216<\/strong>= 64K.<\/p>\r\n \r\n\r\n1.3 Speed<\/strong>\r\n\r\n \r\n

The speed of the memory chip is commonly referred to as its access time.<\/em> The access time of a memory chip varies from a few nanoseconds to hundreds of nanoseconds, depending on the IC technology used in the design and fabrication process.<\/p>\r\n \r\n\r\n \r\n\r\n1.4 ROM (read-only memory):<\/strong>\r\n\r\n \r\n\r\nROM is a type of memory that does not lose its contents when the power is turned off. For this reason,\r\n\r\n \r\n\r\nROM is also called nonvolatile<\/strong> memory. There are different types of read-only memory. They are:\r\n\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 PROM\r\n\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 EPROM\r\n\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 EEPROM\r\n\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 Flash EPROM\r\n\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 Mask ROM\r\n\r\n \r\n\r\n1.5 PROM (programmable ROM) and OTP:<\/strong>\r\n\r\n \r\n

For every bit of the PROM, there exists a fuse. PROM is programmed by blowing the fuses. If the information burned into PROM is wrong, that PROM must be discarded since its internal fuses are blown permanently.<\/p>\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 PROM is also referred to as an OTP (one-time programmable) device.\r\n\r\n \r\n\r\n\u2713\u00a0\u00a0\u00a0\u00a0 Programming ROM, also called burning ROM, requires special equipment called a ROM burner or ROM programmer.\r\n\r\n \r\n\r\n \r\n\r\n1.6 EPROM(Erasable Programmable ROM) and UV-EPROM:<\/strong>\r\n\r\n \r\n\r\nEPROM was invented to allow making changes in the contents of PROM after it is burnt.\r\n\r\n \r\n

\u2713 In EPROM, one can program the memory chip and erase it thousands of times. A widely used EPROM is called UVEPROM.<\/p>\r\n \r\n\r\n\u2713 UV stands for ultra-violet.<\/span>\r\n\r\n<\/div>\r\n \r\n

The only problem with UV-EPROM is that erasing its contents can take up to 20 minutes. All UV-EPROM chips have a window that is used to shine ultraviolet (UV) radiation to erase its contents. The major disadvantage of UV-EPROM, is that it cannot be programmed while in the system board.<\/p>\r\n \r\n\r\n1.7 EEPROM(Electrically Erasable Programmable ROM) :<\/strong>\r\n\r\n \r\n

EEPROM has several advantages over EPROM. Its method of erasure is electrical and therefore instant, as opposed to the 20-minute erasure time required for UVEPROM. One can select which byte is to be erased, in contrast to UV-EPROM, in which the entire contents of the ROM are erased. One can program and erase its contents while it is still in the system board. EEPROM does not require an external erasure and programming device. The designer incorporates into the system board the circuitry to program the EEPROM.<\/p>\r\n \r\n\r\n1.8 RAM(Random Access Memory) :<\/strong>\r\n\r\n \r\n

RAM memory is called volatile memory since cutting off the power to the IC will result in the loss of data. Sometimes RAM is also referred to as RAWM (read and write memory), in contrast to ROM, which cannot be written to.<\/p>\r\n \r\n\r\nThere are three types of RAM:\r\n\r\n \r\n\r\n\u2713 Static RAM (SRAM),\r\n\r\n\u2713 NV-RAM (nonvolatile RAM), and\r\n\r\n\u2713 Dynamic RAM (DRAM).\r\n\r\n \r\n\r\n1.9.1 SRAM (static RAM) :<\/em><\/strong>\r\n\r\n \r\n

Storage cells in static RAM memory are made of flip-flops. Therefore, they do not require refreshing in order to keep their data. This is in contrast to DRAM.<\/p>\r\n \r\n\r\n\"\"\r\n\r\n1.9.2 DRAM (Dynamic RAM):<\/em><\/strong>\r\n\r\n \r\n

DRAM (dynamic RAM) uses a capacitor to store each bit. It requires constant refreshing due to leakage of charge from the capacitor.<\/span><\/p>\r\n \r\n\r\nPackaging issue in DRAM:<\/strong>\r\n\r\n \r\n

In DRAM there is a problem of packing a large number of cells into a single chip with the normal number of pins assigned to addresses. To solve this problem, multiplexing is used. Column address and row address are multiplexed onto the same pins here. Row Address Strobe (RAS) and Column Address Strobe (CAS) are used to indicate whether the row address or the column address are carried on the address lines. This requires only half the number of address pins. As shown in Fig 1.3, in the 256Kx1 DRAM, the address lines A0 to A8 are used along with RAS and CAS to carry row address and column address respectively. Thus with 9 pins we can address 256K locations<\/p>\r\n \r\n\r\n\"\"\r\n\r\n \r\n\r\n1.9.3 Non-volatile random-access memory (NVRAM)<\/em><\/strong>\r\n\r\n \r\n

NVRAM is random-access memory <\/a>that retains its information when power is turned off (non-volatile)<\/a>. This is in contrast to dynamic, random-access memory(DRAM) and static random-access memory<\/a> (SRAM), which both maintain data only for as long as power is applied. The best-known form of NVRAM memory today is flash memory.<\/a><\/p>\r\n \r\n\r\n Memory Address Decoding<\/strong>\r\n\r\n \r\n

Large capacity memories are constructed using smaller blocks of memories. Hence the required block has to be selected based on the memory address. This is done by decoding the memory addresses. There are three ways to generate a memory block selector a) using simple logic gates, b) using a decoder, such as, 74LS138, and c) using the programmable logic. We discuss the first two methods here.<\/p>\r\n \r\n\r\n2.1 Decoder using NAND and other gates<\/strong>\r\n\r\n \r\n

Figure 2.1 shows 4K*8 memory chip Decoder with NAND and other gates. There are twelve address lines from A0-A11 for accessing the location and data lines from D0-D7.CS, RD and WR are the control signals. CS is the Chip select pin which is enabled by the address lines A15 to A12. If RD is set to 0, then we can read the Content, and if WR is set to 0, we can write into the chip. The chip select can be enabled by giving the address lines A15-A12=0011. This will correspond to an address range of 3000 to 3FFFH.<\/p>\r\n \r\n\r\n\"\"\r\n\r\n2.2 74LS138, 3-8 Decoder<\/strong>\r\n\r\n \r\n

The 3 inputs A, B, and C generate 8 active low outputs Y0 \u2013 Y7. O\/P Y is connected to CS of a memory chip as shown in figure 2.2. It selects 8 memory blocks. A,B and C select which o\/p is to be activated. Additional i\/p\u2019s G2A and G2B are both active low, and G1 is active high. If any one of the inputs G1, G2A, or G2B is not connected to an address signal, they must be activated permanently either by Vcc or ground, depending on the activation level.<\/p>\r\n \r\n\r\n\"\"\r\n

\r\n\r\n \r\n\r\n2.3. Accessing On-chip and off-chip code ROM<\/strong>\r\n\r\n<\/div>\r\n

In this section we are going to discuss the interfacing of 8031 microcontroller with external ROM. EA pin of 8031 microcontroller is connected to Vcc to indicate that the program code is stored in the C's on-chip ROM. Figure 2.3 shows the on-chip and off-chip program code access.<\/p>\r\n \r\n

To indicate that the program code is stored in external ROM, this pin must be connected to GND.<\/p>\r\n \r\n

If we have EA= Gnd, then it refers to the on-chip Program. If EA=VCC, it refers to the off-chip program. However, , upon reset the 8051 executes the on-chip program first. Then, when it reaches the end of the on-chip ROM, it switches to external ROM for the rest of the program code.<\/p>\r\n \r\n\r\n\"\"\r\n

\r\n\r\n \r\n\r\n2.3.1 8051 Interfacing with External ROM<\/strong>\r\n\r\n \r\n

CPU gives the address of the data required. Decoding circuit has to locate the selected memory block. Memory chips have CS (chip select) pin, which must be activated for the memory\u2019s contents to be accessed.<\/p>\r\n \r\n

The pins 29, 30 and 31 of the 8051 microcontroller (shown in Fig. 2.4) are used to provide the memory interface related signals.<\/p>\r\n \r\n

Pin 29<\/strong>: PSEN-If we use an external ROM then this pin should have a logic 0 which indicates that the Microcontroller should read data from memory.<\/p>\r\n \r\n

Pin 30<\/strong>: ALE\/PROG- This pin is used for ALE that is Address Latch Enable. This pin is used to demultiplex address and data lines. This pin also gives program pulse input during programming of EPROM.<\/p>\r\n \r\n

Pin 31<\/strong>: EA\/VPP- If we have to use multiple memories then applying logic 1 to this pin instructs 8051 to read data from both memories - first internal and then external.<\/p>\r\n\r\n<\/div>\r\n\"\"\r\n

\r\n\r\n2.3.2 Steps to be followed when connecting external memory<\/em><\/strong>\r\n\r\n \r\n

CPU data bus is connected directly to the data pins of the memory chip. Control signals RD (read) and WR (memory write) from the CPU are connected to the OE (output enable) and WE (write enable) pins of the memory chip. The lower bits of the address from the CPU are connected directly to the memory chip address pins. The upper ones are used to activate the CS pin of the memory chip.<\/p>\r\n \r\n\r\nP0 and P2 role in providing addresses:<\/strong>\r\n\r\n \r\n\r\n\u2022 The PC (program counter) of the 8031\/51 is 16-bit, it is capable of accessing up to 64K bytes of program code.\r\n\r\n \r\n\r\n\u2022 16 bit address is provided by port 0 and port 2 to access external memory.\r\n\r\n \r\n\r\n\u2022 P0 provides the lower 8 bit address A0 \u2013 A7.\r\n\r\n \r\n\r\n\u2022 P2 provides the upper 8 bit address A8 \u2013 A15.\r\n\r\n \r\n\r\n\u2022 P0 is also used to provide the 8-bit data D0\u2013D7.\r\n\r\n \r\n\r\n\u2022 P0.0 \u2013 P0.7 are used for both the address\u00a0 and data paths (address\/data multiplexing).\r\n\r\n \r\n\r\nThe ALE signal is used to determine whether P0 carries address or data signals.\r\n\r\n \r\n\r\n \r\n\r\n2.3.2.1 ALE (Address Latch Enable):<\/em><\/strong>\r\n\r\n \r\n\r\n\u2022 ALE (address latch enable) pin is an output pin for 8031\/51.\r\n\r\n \r\n\r\n\u2022 When ALE = 0, then 8031 uses P0 for the data path.\r\n\r\n<\/div>\r\n\u00a0 \u00a0 \u2022 W hen ALE = 1, then 8031 uses P0 for the address path.<\/span>\r\n

\r\n\r\n\u00a0 \u00a0 \u2022 To extract the addresses from the P0 pins, it is connected to 74LS373 D Latch. The pins and structure of 74LS373 are shown in figure 2.5.\r\n\r\n \r\n

\u2022 Separation of address and data can be obtained by using 74LS373. Figure 2.6 shows the address\/data de-multiplexing. In the figure it is noted that when ALE=0 and P0 is used as a data bus, sending data out or bringing data in. Whenever the 8031\/8051 wants to use P0 as an address bus, it puts the addresses A0-A7 on the P0 pins and activates ALE=1 to indicate that P0 has the addresses.<\/p>\r\n \r\n\r\n\"\"\r\n\r\n<\/div>\r\n\"\"\r\n

\r\n

\u2022PSEN is the Program store enable and it is an o\/p signal. It is used to handle the Program memory and Data memory. PSEN is connected to OE pin of Program ROM. PSEN and EA of 8031\/8051 are used to access external ROM. If the Memory is the Program memory then PSEN is connected to External Memory which reads the Program from the external Memory. If EA is connected to Ground then external ROM is accessed. If EA is connected to VCC, then the internal ROM is accessed. Figure 2.7 shows the Data, Address and Control buses for the 8031\/8051.<\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n\"\"\r\n\r\n\"\"\r\n\r\n \r\n

While accessing the address, ALE should be equal to one, and for accessing the data ALE should be equal to zero. When accessing the external program memory, PSEN pin of 8051\/8031 should be connected to the chip enable (CE and OE) pins of external memory, as shown in Figure 2.8.<\/p>\r\n \r\n\r\n2.44 8051 Data Memory Space<\/strong>\r\n\r\n<\/div>\r\nThe 8051 has 128 bytes of address space.<\/span>\r\n