{"id":132,"date":"2018-07-26T11:14:05","date_gmt":"2018-07-26T11:14:05","guid":{"rendered":"http:\/\/csp13.epgpbooks.inflibnet.ac.in\/?post_type=chapter&p=132"},"modified":"2018-08-10T12:05:03","modified_gmt":"2018-08-10T12:05:03","slug":"interrupt-handling","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/chapter\/interrupt-handling\/","title":{"rendered":"Interrupt Handling"},"content":{"raw":"
\r\n\r\n \r\n\r\n1. Interrupt<\/strong>\r\n\r\n \r\n

An interrupt is the occurrence of a condition--an event -- that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler).<\/p>\r\n \r\n\r\n\"\"\r\n\r\n \r\n

Figure.1 shows ISR. In which first part of the figure shows main program is interrupted. The next part shows main program is paused and ISR is providing service to interrupt and when it finishes main program is restored.<\/p>\r\n \r\n\r\n1.1 Interrupt Vs Polling<\/strong>\r\n\r\n \r\n

Interrupt - is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.<\/p>\r\n \r\n\r\nServing a device can be done in two ways-\r\n\r\n \r\n\r\n1)\u00a0 Interrupt\r\n\r\n2)\u00a0 Polling\r\n\r\n \r\n

Interrupt<\/strong>: Here, a device needs service, and the device notifies the microcontroller by sending it an interrupt signal. After receiving an interrupt signal, the microcontroller stops whatever it is doing and serves the device. Program associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.<\/p>\r\n \r\n

Polling<\/strong>: In this, the microcontroller continuously monitors the status of the given devices. When the conditions are met, (that is, if the device needs some service) it performs the\u00a0service. Next, it moves on to monitor the next device. It continues in this fashion until everyone is serviced.<\/span><\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\nInterrupt is preferred over polling for the following reasons:\r\n\r\n \r\n\r\n\u25cf\u00a0 Polling is not efficient, because it wastes much of the microcontroller\u2019s time by checking devices that do not need service.\r\n\r\n \r\n

\u25cf Interrupt can serve many devices; and each device can get the service of microcontroller based on priority.<\/p>\r\n \r\n

\u25cf In polling there is no priority, only on round robin basis they can get the attention of the microcontroller.<\/p>\r\n \r\n

\u25cf In interrupt, a microcontroller can also ignore a device\u2019s request for service, this is not possible in the polling method.<\/p>\r\n \r\n\r\n2.\u00a0 <\/strong>Interrupt Service Routine(ISR):<\/strong>\r\n\r\n \r\n

Each interrupt has an <\/span>interrupt service routine<\/strong> (ISR), or is called, the microcontroller runs the interrupt service location in memory that holds the address of the ISR.<\/span><\/p>\r\n \r\n

interrupt handler. <\/strong>When an interrupt routine. Every interrupt has a fixed<\/span><\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n\"\"\r\n\r\n \r\n

In the above table, 8051 interrupts are listed. When the reset interrupt is given through 9th pin system is reset. At that time the service starts from 0000 location. The two port pins P3.2 and P3.3 are external hardware interrupts.<\/p>\r\n \r\n\r\n2.1 Steps followed when interrupt occurs<\/strong>\r\n\r\n \r\n\r\nThe group of memory locations that hold the addresses of ISRs is called an interrupt vector table.\r\n\r\n \r\n\r\n1. Microcontroller completes the instruction it is executing and saves the address of the next instruction (PC) on the stack.\r\n\r\n \r\n\r\n2. Saves the current status of the system internally in stack.\r\n\r\n \r\n\r\n3. System starts executing ISR routine, where as the starting address of that ISR routine is referred from interrupt vector table\r\n\r\n<\/div>\r\n

\r\n\r\n\u00a0 4. The microcontroller gets the location of the ISR from the interrupt vector table and control is transferred to that location. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI (return from interrupt).\r\n\r\n \r\n\r\n5. After executing the RETI instruction, the microcontroller returns to the place where it was interrupted.\r\n\r\n \r\n\r\n6. First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC.\r\n\r\n \r\n\r\n7. Restores the system previous program status.\r\n\r\n \r\n\r\n8. Then it starts to execute from that address.\r\n\r\n \r\n\r\n \r\n\r\n2.2 Six Interrupts in the 8051<\/strong>\r\n\r\n \r\n\r\nSix interrupts are allocated as follows\r\n\r\n \r\n

\u2022 Reset \u2013 power-up reset- It is nothing but restarting the system. When the reset is pressed the content of the system is stored and again the memory starts from 0000H.<\/p>\r\n \r\n

\u2022 Two interrupts are set aside for the timers:<\/p>\r\n \r\n

\u2022 One for timer 0 and one for timer 1<\/p>\r\n \r\n

\u2022 Two interrupts are set aside for hardware external interrupts<\/p>\r\n \r\n

\u2022 P3.2 and P3.3 are for the external hardware interrupts INT0 (or EX1), and INT1 (or EX2). For any application, interrupts are needed from outside so that the service can be done based on the input given from outside.<\/p>\r\n \r\n\r\n\u2022 Serial communication has a single interrupt that belongs to both receive and transfer\r\n\r\n \r\n

Interrupt service is ended by noticing return statement (RETI) in ISR routine. There are two returns in instruction set namely RET and RETI. Though it looks similar, there are some differences in them.<\/p>\r\n \r\n\r\n2.2 Differences between RET and RETI:<\/strong>\r\n\r\n \r\n

\u2022 RETI performs an additional task of clearing the interrupt-in-service flag.<\/p>\r\n \r\n

\u2022 RET instead of RETI as the last instruction of the interrupt service routine, it blocks any new interrupt on that pin after the first interrupt, since the pin status would indicate that the interrupt is still being serviced.<\/p>\r\n \r\n

\u2022 RETI instruction clears TF0, TF1, TCON.1, and TCON.3<\/p>\r\n\r\n<\/div>\r\n \r\n\r\n3.1 Example code segment for 8051 Interrupts<\/strong>\r\n\r\n \r\n\r\n\"\"\r\n

\r\n\r\n \r\n

The first line of code indicates that the program starts from the origin 0000H. Then LJMP MAIN means Long jump to main program. Next the Interrupt Service Routine starts from 30H memory location.<\/p>\r\n \r\n\r\n3.2 Enabling and Disabling an Interrupt<\/strong>\r\n\r\n \r\n\r\n\u2022 Upon reset, all interrupts are disabled (masked)\r\n\r\n \r\n\r\n\u25aa\u00a0 None will be responded to by the microcontroller if they are activated.\r\n\r\n \r\n\r\n\u25aa\u00a0 The interrupts must be enabled by software in order for the microcontroller to respond to them\r\n\r\n \r\n

\u25aa There is a register called IE (interrupt enable) that is responsible for enabling (unmasking) and disabling (masking) the interrupts. In IE register, there are 8 bits. Based on those 8 bits, an interrupt can be enabled\/disabled.<\/p>\r\n \r\n\r\n3.3 Steps in Enabling an interrupt:<\/strong>\r\n\r\n \r\n

\u2022 Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take effect.<\/p>\r\n \r\n

\u2022 The value of EA<\/p>\r\n \r\n

\u2022\u00a0 If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are high<\/p>\r\n \r\n

\u2022\u00a0 If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is high EA=1 enable all interrupts, EA=0 disable all interrupts<\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n\"\"\r\n\r\n \r\n

Both the EA pin and the corresponding interrupt pin must be 1 for enabling the particular interrupt. Different methods for enabling interrupts is listed below<\/p>\r\n \r\n\r\nMethod-1\r\n\r\nMOV IE,#10011001 ;enable serial, ;timer 1, EX0\r\n\r\n \r\n\r\nMethod-2 to perform the same task is\r\n\r\nSETB IE.7 <\/span>;EA=1, global enable<\/span>\r\n\r\nSETB IE.4 <\/span>;enable serial interrupt<\/span>\r\n\r\nSETB IE.3\u00a0<\/span>;enable Timer 1 interrupt<\/span>\r\n\r\nSETB IE.0\u00a0<\/span>;enable EX0<\/span>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\nTo disable the interrupts Clear command can be used as shown below\r\n\r\n<\/div>\r\n
\r\n\r\n \r\n\r\nCLR IE.3 ;mask (disable) timer 1 ;interrupt only\r\n\r\nCLR IE.7\u00a0<\/span>;disable all interrupts<\/span>\r\n\r\n<\/div>\r\n
\r\n\r\n \r\n\r\n3.4 Timer Interrupt<\/strong>\r\n\r\n \r\n

For any application which needs timer for a specific purpose and runs for a particular period of time, timer interrupt can be used. The timer interrupt starts and stops the application automatically. The timer flag (TF) is raised when the timer rolls over. Interrupt handles Timer control flag effectively. In polling, System is held up till TF is raised but in Timer Interrupt, System is not locked.<\/p>\r\n \r\n

In Timer Interrupts,<\/span><\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n

\u25cf If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is raised.<\/p>\r\n \r\n

\u25aa The microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR.<\/p>\r\n \r\n

\u25aa\u00a0 In this way, the microcontroller can do other work until it is notified that the timer has rolled over.<\/p>\r\n \r\n\r\n\"\"\r\n\r\n \r\n

Initial count starts from TH and TL register. When the TH and TL register gets FF overflow occurs, then TF0 is set to 1 and the interrupt is automatically enabled.<\/p>\r\n \r\n

\u2022\u00a0 if the timer interrupt is enabled, whenever TF=1, the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR<\/p>\r\n \r\n

\u2022\u00a0 In this way, the microcontroller can do other things until it is notified that the timer has rolled over.<\/p>\r\n \r\n\r\n3.4.1 Timer Interrupt Programming<\/em><\/strong>\r\n\r\n \r\n

Write a program that continuously gets 8-bit data from P0 and sends it to P1 while simultaneously creating a square wave of 200 ms period on pin P2.1. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz.<\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n\"\"\r\n\r\n \r\n

The first line of code indicates that the program is started from 0000H. LJMP indicates that the program has to go for long jump to reach the main loop. The next line indicates that the ISR Routine starts from 000BH.This ISR routine generates a square. The main program is written at position 0030H. In order to set the timer mode, timer 0 mode 2 is set. P0 is used as the input port. Here the square wave generation is for 200 ms, hence 100 ms is for on state and 100 ms for off state. For generating the delay of 100 ms, 92 is used as the count. when the port P0 reaches 0FFH overflow occurs, it means the delay of 92 count is over and the timer is set again. Once the data is stored in P0, it is moved to accumulator and then again the data is moved to port P1. Hence the data is continuously transferred from the Port P0 to P1.<\/p>\r\n \r\n\r\n4. Summary<\/strong>\r\n\r\n \r\n

In this lecture different concept of Interrupts and difference between interrupt and polling methods are discussed. The steps for executing the interrupts in 8051 are also discussed. The assembly code for 8051 Timer Interrupt Programming has been explained.<\/p>\r\n \r\n

5. References<\/strong><\/p>\r\n \r\n

\u00a01.\u00a0<\/strong>Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D. McKinlay, \u201cThe 8051 Microcontroller and Embedded Systems Using Assembly and C -Second Edition\u201d.<\/span><\/p>\r\n\r\n<\/div>","rendered":"

\n

 <\/p>\n

1. Interrupt<\/strong><\/p>\n

 <\/p>\n

An interrupt is the occurrence of a condition–an event — that cause a temporary suspension of a program while the event is serviced by another program (Interrupt Service Routine ISR or Interrupt Handler).<\/p>\n

 <\/p>\n

\"\"<\/p>\n

 <\/p>\n

Figure.1 shows ISR. In which first part of the figure shows main program is interrupted. The next part shows main program is paused and ISR is providing service to interrupt and when it finishes main program is restored.<\/p>\n

 <\/p>\n

1.1 Interrupt Vs Polling<\/strong><\/p>\n

 <\/p>\n

Interrupt – is an external or internal event that interrupts the microcontroller to inform it that a device needs its service.<\/p>\n

 <\/p>\n

Serving a device can be done in two ways-<\/p>\n

 <\/p>\n

1)\u00a0 Interrupt<\/p>\n

2)\u00a0 Polling<\/p>\n

 <\/p>\n

Interrupt<\/strong>: Here, a device needs service, and the device notifies the microcontroller by sending it an interrupt signal. After receiving an interrupt signal, the microcontroller stops whatever it is doing and serves the device. Program associated with the interrupt is called the interrupt service routine (ISR) or interrupt handler.<\/p>\n

 <\/p>\n

Polling<\/strong>: In this, the microcontroller continuously monitors the status of the given devices. When the conditions are met, (that is, if the device needs some service) it performs the\u00a0service. Next, it moves on to monitor the next device. It continues in this fashion until everyone is serviced.<\/span><\/p>\n<\/div>\n

\n

 <\/p>\n

Interrupt is preferred over polling for the following reasons:<\/p>\n

 <\/p>\n

\u25cf\u00a0 Polling is not efficient, because it wastes much of the microcontroller\u2019s time by checking devices that do not need service.<\/p>\n

 <\/p>\n

\u25cf Interrupt can serve many devices; and each device can get the service of microcontroller based on priority.<\/p>\n

 <\/p>\n

\u25cf In polling there is no priority, only on round robin basis they can get the attention of the microcontroller.<\/p>\n

 <\/p>\n

\u25cf In interrupt, a microcontroller can also ignore a device\u2019s request for service, this is not possible in the polling method.<\/p>\n

 <\/p>\n

2.\u00a0 <\/strong>Interrupt Service Routine(ISR):<\/strong><\/p>\n

 <\/p>\n

Each interrupt has an <\/span>interrupt service routine<\/strong> (ISR), or is called, the microcontroller runs the interrupt service location in memory that holds the address of the ISR.<\/span><\/p>\n

 <\/p>\n

interrupt handler. <\/strong>When an interrupt routine. Every interrupt has a fixed<\/span><\/p>\n<\/div>\n

\n

\"\"<\/p>\n

 <\/p>\n

In the above table, 8051 interrupts are listed. When the reset interrupt is given through 9th pin system is reset. At that time the service starts from 0000 location. The two port pins P3.2 and P3.3 are external hardware interrupts.<\/p>\n

 <\/p>\n

2.1 Steps followed when interrupt occurs<\/strong><\/p>\n

 <\/p>\n

The group of memory locations that hold the addresses of ISRs is called an interrupt vector table.<\/p>\n

 <\/p>\n

1. Microcontroller completes the instruction it is executing and saves the address of the next instruction (PC) on the stack.<\/p>\n

 <\/p>\n

2. Saves the current status of the system internally in stack.<\/p>\n

 <\/p>\n

3. System starts executing ISR routine, where as the starting address of that ISR routine is referred from interrupt vector table<\/p>\n<\/div>\n

\n

\u00a0 4. The microcontroller gets the location of the ISR from the interrupt vector table and control is transferred to that location. It starts to execute the interrupt service subroutine until it reaches the last instruction of the subroutine which is RETI (return from interrupt).<\/p>\n

 <\/p>\n

5. After executing the RETI instruction, the microcontroller returns to the place where it was interrupted.<\/p>\n

 <\/p>\n

6. First, it gets the program counter (PC) address from the stack by popping the top two bytes of the stack into the PC.<\/p>\n

 <\/p>\n

7. Restores the system previous program status.<\/p>\n

 <\/p>\n

8. Then it starts to execute from that address.<\/p>\n

 <\/p>\n

 <\/p>\n

2.2 Six Interrupts in the 8051<\/strong><\/p>\n

 <\/p>\n

Six interrupts are allocated as follows<\/p>\n

 <\/p>\n

\u2022 Reset \u2013 power-up reset- It is nothing but restarting the system. When the reset is pressed the content of the system is stored and again the memory starts from 0000H.<\/p>\n

 <\/p>\n

\u2022 Two interrupts are set aside for the timers:<\/p>\n

 <\/p>\n

\u2022 One for timer 0 and one for timer 1<\/p>\n

 <\/p>\n

\u2022 Two interrupts are set aside for hardware external interrupts<\/p>\n

 <\/p>\n

\u2022 P3.2 and P3.3 are for the external hardware interrupts INT0 (or EX1), and INT1 (or EX2). For any application, interrupts are needed from outside so that the service can be done based on the input given from outside.<\/p>\n

 <\/p>\n

\u2022 Serial communication has a single interrupt that belongs to both receive and transfer<\/p>\n

 <\/p>\n

Interrupt service is ended by noticing return statement (RETI) in ISR routine. There are two returns in instruction set namely RET and RETI. Though it looks similar, there are some differences in them.<\/p>\n

 <\/p>\n

2.2 Differences between RET and RETI:<\/strong><\/p>\n

 <\/p>\n

\u2022 RETI performs an additional task of clearing the interrupt-in-service flag.<\/p>\n

 <\/p>\n

\u2022 RET instead of RETI as the last instruction of the interrupt service routine, it blocks any new interrupt on that pin after the first interrupt, since the pin status would indicate that the interrupt is still being serviced.<\/p>\n

 <\/p>\n

\u2022 RETI instruction clears TF0, TF1, TCON.1, and TCON.3<\/p>\n<\/div>\n

 <\/p>\n

3.1 Example code segment for 8051 Interrupts<\/strong><\/p>\n

 <\/p>\n

\"\"<\/p>\n

\n

 <\/p>\n

The first line of code indicates that the program starts from the origin 0000H. Then LJMP MAIN means Long jump to main program. Next the Interrupt Service Routine starts from 30H memory location.<\/p>\n

 <\/p>\n

3.2 Enabling and Disabling an Interrupt<\/strong><\/p>\n

 <\/p>\n

\u2022 Upon reset, all interrupts are disabled (masked)<\/p>\n

 <\/p>\n

\u25aa\u00a0 None will be responded to by the microcontroller if they are activated.<\/p>\n

 <\/p>\n

\u25aa\u00a0 The interrupts must be enabled by software in order for the microcontroller to respond to them<\/p>\n

 <\/p>\n

\u25aa There is a register called IE (interrupt enable) that is responsible for enabling (unmasking) and disabling (masking) the interrupts. In IE register, there are 8 bits. Based on those 8 bits, an interrupt can be enabled\/disabled.<\/p>\n

 <\/p>\n

3.3 Steps in Enabling an interrupt:<\/strong><\/p>\n

 <\/p>\n

\u2022 Bit D7 of the IE register (EA) must be set to high to allow the rest of register to take effect.<\/p>\n

 <\/p>\n

\u2022 The value of EA<\/p>\n

 <\/p>\n

\u2022\u00a0 If EA = 1, interrupts are enabled and will be responded to if their corresponding bits in IE are high<\/p>\n

 <\/p>\n

\u2022\u00a0 If EA = 0, no interrupt will be responded to, even if the associated bit in the IE register is high EA=1 enable all interrupts, EA=0 disable all interrupts<\/p>\n<\/div>\n

\n

\"\"<\/p>\n

 <\/p>\n

Both the EA pin and the corresponding interrupt pin must be 1 for enabling the particular interrupt. Different methods for enabling interrupts is listed below<\/p>\n

 <\/p>\n

Method-1<\/p>\n

MOV IE,#10011001 ;enable serial, ;timer 1, EX0<\/p>\n

 <\/p>\n

Method-2 to perform the same task is<\/p>\n

SETB IE.7 <\/span>;EA=1, global enable<\/span><\/p>\n

SETB IE.4 <\/span>;enable serial interrupt<\/span><\/p>\n

SETB IE.3\u00a0<\/span>;enable Timer 1 interrupt<\/span><\/p>\n

SETB IE.0\u00a0<\/span>;enable EX0<\/span><\/p>\n<\/div>\n

\n

 <\/p>\n

To disable the interrupts Clear command can be used as shown below<\/p>\n<\/div>\n

\n

 <\/p>\n

CLR IE.3 ;mask (disable) timer 1 ;interrupt only<\/p>\n

CLR IE.7\u00a0<\/span>;disable all interrupts<\/span><\/p>\n<\/div>\n

\n

 <\/p>\n

3.4 Timer Interrupt<\/strong><\/p>\n

 <\/p>\n

For any application which needs timer for a specific purpose and runs for a particular period of time, timer interrupt can be used. The timer interrupt starts and stops the application automatically. The timer flag (TF) is raised when the timer rolls over. Interrupt handles Timer control flag effectively. In polling, System is held up till TF is raised but in Timer Interrupt, System is not locked.<\/p>\n

 <\/p>\n

In Timer Interrupts,<\/span><\/p>\n<\/div>\n

\n

 <\/p>\n

\u25cf If the timer interrupt in the IE register is enabled, whenever the timer rolls over, TF is raised.<\/p>\n

 <\/p>\n

\u25aa The microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR.<\/p>\n

 <\/p>\n

\u25aa\u00a0 In this way, the microcontroller can do other work until it is notified that the timer has rolled over.<\/p>\n

 <\/p>\n

\"\"<\/p>\n

 <\/p>\n

Initial count starts from TH and TL register. When the TH and TL register gets FF overflow occurs, then TF0 is set to 1 and the interrupt is automatically enabled.<\/p>\n

 <\/p>\n

\u2022\u00a0 if the timer interrupt is enabled, whenever TF=1, the microcontroller is interrupted in whatever it is doing, and jumps to the interrupt vector table to service the ISR<\/p>\n

 <\/p>\n

\u2022\u00a0 In this way, the microcontroller can do other things until it is notified that the timer has rolled over.<\/p>\n

 <\/p>\n

3.4.1 Timer Interrupt Programming<\/em><\/strong><\/p>\n

 <\/p>\n

Write a program that continuously gets 8-bit data from P0 and sends it to P1 while simultaneously creating a square wave of 200 ms period on pin P2.1. Use Timer 0 to create the square wave. Assume that XTAL = 11.0592 MHz.<\/p>\n<\/div>\n

\n

\"\"<\/p>\n

 <\/p>\n

The first line of code indicates that the program is started from 0000H. LJMP indicates that the program has to go for long jump to reach the main loop. The next line indicates that the ISR Routine starts from 000BH.This ISR routine generates a square. The main program is written at position 0030H. In order to set the timer mode, timer 0 mode 2 is set. P0 is used as the input port. Here the square wave generation is for 200 ms, hence 100 ms is for on state and 100 ms for off state. For generating the delay of 100 ms, 92 is used as the count. when the port P0 reaches 0FFH overflow occurs, it means the delay of 92 count is over and the timer is set again. Once the data is stored in P0, it is moved to accumulator and then again the data is moved to port P1. Hence the data is continuously transferred from the Port P0 to P1.<\/p>\n

 <\/p>\n

4. Summary<\/strong><\/p>\n

 <\/p>\n

In this lecture different concept of Interrupts and difference between interrupt and polling methods are discussed. The steps for executing the interrupts in 8051 are also discussed. The assembly code for 8051 Timer Interrupt Programming has been explained.<\/p>\n

 <\/p>\n

5. References<\/strong><\/p>\n

 <\/p>\n

\u00a01.\u00a0<\/strong>Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D. McKinlay, \u201cThe 8051 Microcontroller and Embedded Systems Using Assembly and C -Second Edition\u201d.<\/span><\/p>\n<\/div>\n","protected":false},"author":2,"menu_order":12,"template":"","meta":{"pb_show_title":"on","pb_short_title":"","pb_subtitle":"","pb_authors":["dr-k-vani"],"pb_section_license":""},"chapter-type":[],"contributor":[58],"license":[],"class_list":["post-132","chapter","type-chapter","status-publish","hentry","contributor-dr-k-vani"],"part":3,"_links":{"self":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/132","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters"}],"about":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/types\/chapter"}],"author":[{"embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/users\/2"}],"version-history":[{"count":5,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/132\/revisions"}],"predecessor-version":[{"id":447,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/132\/revisions\/447"}],"part":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/parts\/3"}],"metadata":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapters\/132\/metadata\/"}],"wp:attachment":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/media?parent=132"}],"wp:term":[{"taxonomy":"chapter-type","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/pressbooks\/v2\/chapter-type?post=132"},{"taxonomy":"contributor","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/contributor?post=132"},{"taxonomy":"license","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp13\/wp-json\/wp\/v2\/license?post=132"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}