13 Interrupt Handling and Assembly Programming

Dr K. Vani

 

In this lecture configuring different interrupts of 8051 will be discussed. Assembly programs will be written for creating external interrupts and to establish interrupt based serial port communication. Interrupt priorities and its importance will also be discussed.

 

1.External Interrupts

 

The 8051 has two external hardware interrupts. Pin 12 (P3.2) and pin 13 (P3.3) of the 8051 designated as INT0 and INT1 and used as external hardware interrupts. The interrupt vector table locations 0003H and 0013H are set aside for INT0 and INT1. There are two activation levels for the external hardware interrupts. One is level-triggered and other one is edge-triggered interrupts.

 

 

1.1 Level-Triggered Interrupt

 

INT0 and INT1 pins are normally high in level trigger mode. Low-level signal on INT0 or INT1 triggers the interrupt. Once the interrupt occurs, the microcontroller stops whatever it is doing and jumps to the interrupt vector table to service that interrupt. The low-level signal is to be removed before the execution of the last instruction of the ISR, i.e., RETI. If the low level signal is not removed, it results in another interrupt being generated. This is called a level-triggered or level activated interrupt and is the default mode upon reset of the 8051.

 

1.2 Programming External Hardware Interrupts

 

Assume that the INT1 pin is connected to a switch that is normally high. Whenever it goes low, it should turn on an LED. The LED is connected to P1.3 and is normally off. When it is turned on it should stay on for a fraction of a second. As long as the switch is pressed low, the LED should stay on. Following is the assembly program for implementing this.

 

1.3 Sampling Low Level-Triggered Interrupt

 

P3.2 and P3.3 are used for normal I/O unless the INT0 and INT1 bits in the IE register are enabled. After the hardware interrupts are enabled, the controller keeps sampling the INTn pin for a low-level signal once each machine cycle. The pin must be held in a low state until the start of the execution of ISR. If the INTn pin is brought back to a logic high before the start of the execution of ISR, there will be no interrupt. If INTn pin is left at a logic low after the RETI instruction of the ISR, another interrupt will be activated after one instruction is executed. To ensure the activation of the hardware interrupt at the INTn pin, the duration of the low-level signal is around 4 machine cycles, but no more. This is due to the fact that the level-triggered interrupt is not latched. Thus the pin must be held in a low state until the start of the ISR execution.

 

 

1.4 Edge-triggered interrupts

 

To make INT0 and INT1 edge-triggered interrupts, we must program the bits of the TCON register. The TCON register holds the IT0 and IT1 flag bits that determine level- or edge-triggered mode of the hardware interrupt. IT0 and IT1 are bits D0 and D2 of TCON (TCON.0 and TCON.2 ). To make INT0 and INT1 edge triggered interrupts, we must program the bits of the TCON register. Figure.3 shows the bit details of IE register. This register should be set first to utilize interrupt for application development.

 

1.5 Program

 

Assuming that INT1 is connected to a pulse generator. Write a program in which the falling edge of the pulse will send a high to P 1.3, which is connected to an LED.

 

 

2. Sampling the edge-triggered interrupt

 

The external source must be held high for at least one machine cycle, and then held low for at least one machine cycle. The falling edge of pins INT0 and INT1 are latched by the 8051 and are held by the TCON.1 and TCON.3 bits of TCON register. It functions as interrupt-in-service flag. It indicates that the interrupt is being serviced now. On this INTn pin, no new interrupt will be responded to until this service is finished . When the ISRs are finished, TCON.1 and TCON.3 are cleared. The interrupt is finished and the 8051 is ready to respond to another interrupt on that pin. During the time that the interrupt service routine is being executed, the INTn pin is ignored, no matter how many times it makes a high-to-low transition.

 

3. Serial communication Interrupt

 

RETI clears the corresponding bit in TCON register (TCON.1 or TCON.3). There is no need for instruction CLR TCON.1 before RETI in the ISR associated with INT0. TI (transfer interrupt) is raised when the stop bit is transferred. Indicating that the SBUF register is ready to transfer the next byte. RI (received interrupt) is raised when the stop bit is received. Indicating that the received byte needs to be picked up before it is lost (overrun) by new incoming serial data.

 

In the 8051 there is only one interrupt set aside for serial communication. It is used to both send and receive data . If the interrupt bit in the IE register (IE.4) is enabled, when RI or TI is raised. The 8051 gets interrupted and jumps to memory location 0023H to execute the ISR. In that ISR we must examine the TI and RI flags to see which one caused the interrupt and respond accordingly.

 

3.1 Use of Serial COM in the 8051

 

The serial interrupt is used mainly for receiving data and is used for sending data serially. This is like getting a telephone call in which we need a ring to be notified. If we need to make a phone call there are other ways to remind ourselves and there is no need for ringing. However in receiving the phone call, we must respond immediately no matter what we are doing or we will miss the call. So in serial communication though we have only one interrupt for sending as well as receiving, importance is given for receiving data serially. This is to avoid missing serial data from outside devices.

Example assembly program for serial communication is given below.

 

3.2 Interrupt Flag Bits for 8051

 

The TCON register holds four of the interrupt flags in the 8051. The SCON register has the RI and TI flags.

 

 

3.2.1 Interrupt Priority

 

When the 8051 is powered up, the priorities are assigned. Priority of interrupt is shown in Table.3. In reality, the priority scheme is nothing but an internal polling sequence in which the 8051 polls the interrupts in the sequence listed & responds accordingly.

 

If two requests of different priority Levels are received simultaneously, the request of higher priority level is serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced.

 

 

3.3 Changing the Priority

 

Priority can be changed by using the control bits in the Interrupt Priority register. To give a higher priority to any of the interrupts, make the corresponding bit in the IP register high. When two or more interrupt bits in the IP register are set to high, interrupt which has the highest priority will be served .

 

3.4 Interrupt Control System

 

Interrupt control system shown below in figure.7 explains how interrupts and its priorities can be achieved using hardware. By setting bit 1 in IE register will connects / shorts inside the switches . The interrupts polled will be recognised and served based on priorities.

 

Example: If interrupts INT0, TF1, and INT1 are activated at the same time, in what sequence would the interrupts be serviced? Assume priority levels were set by the power-up reset and the external hardware interrupts are edge triggered.

 

Solution:

 

First external interrupt 0(IE0) is serviced, next external interrupt 1 (IE1) is serviced and last timer 1(TF1) is serviced.

 

Example: Assume that after reset, the interrupt priority register is set by the instruction

 

MOV IP, #00011000B. Discuss the sequence in which the interrupts are serviced.

 

Solution:

 

The priority of interrupts served is as follows:

Example: Clear P2.7 when external interrupt 0 occurs and set P2.7 when external interrupt 1 occurs.

 

 

 

4. Summary

 

In this lecture, we have discussed the configuration of different interrupts of 8051. Assembly code for 8051 external hardware interrupt programming has been written. Assembly code for 8051 Serial Communication using interrupt programming has also been written. 8051 interrupt priorities have also been discussed.

 

5. References

  1. Muhammad Ali Mazidi, Janice Gillispie Mazidi, Rolin D. McKinlay, “The 8051 Microcontroller and Embedded Systems Using Assembly and C -Second Edition”, New Delhi(2000).