{"id":258,"date":"2018-07-20T09:39:31","date_gmt":"2018-07-20T09:39:31","guid":{"rendered":"http:\/\/csp10.epgpbooks.inflibnet.ac.in\/?post_type=chapter&p=258"},"modified":"2018-07-20T09:40:40","modified_gmt":"2018-07-20T09:40:40","slug":"simple-code-generator-and-register-allocation","status":"publish","type":"chapter","link":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/chapter\/simple-code-generator-and-register-allocation\/","title":{"rendered":"Simple code generator and Register allocation"},"content":{"raw":"
\r\n

In this module we will try to learn the simple code generator algorithm. We shall also discuss the data structures involved in the simple code generator algorithm. We will conclude this module by understanding the algorithms for register allocation.<\/p>\r\n \r\n\r\n30.1 Simple Code Generator<\/strong>\r\n\r\n \r\n

The simple code generator algorithm generates target code for a sequence of three-address statements. The code generator algorithm works by considering individually all the basic blocks. It uses the next-use information to decide on whether to keep the computation in the register or move it to a variable so that the register could be reused. The computation of next-use information is explained in the previous module. We assume that for each operator in the input statement there is a target- language operator. It uses new function getreg()<\/em> to assign registers to variables. The algorithm for code generation initially checks if operands to three-address code are available in registers. After computing the results of two operations, the results are kept in registers till the result is required by another computation or register is kept up to a procedure call or end of block to avoid errors.<\/p>\r\n \r\n\r\nFor example, consider the following instruction:\r\n\r\n \r\n\r\n\u2022\u00a0\u00a0\u00a0\u00a0\u00a0 a := b+c\r\n\r\n \r\n\r\nThe following sequence would be followed by the code generator algorithm:\r\n

\u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 The algorithm initially checks if \u2018b\u2019 and \u2018c\u2019 are in registers Ri, Rj. If available then the instruction ADD Ri, Rj is generated and this costs 1 and the result is stored in Rj<\/p>\r\n\u2022\u00a0\u00a0\u00a0\u00a0\u00a0 If \u2018b\u2019 alone is in register and \u2018c\u2019 is not in the register, then the instruction ADD c, Ri is generated to a cost of 2\r\n\r\n\u2022\u00a0\u00a0\u00a0\u00a0\u00a0 MOV a, Rj is issued to move the computation to \u2018a\u2019.\r\n\r\n \r\n

The issues that need to be resolved are how to get the registers. If the registers are free then there is no issue. If the registers are all occupied, we must free an existing register. Will the instruction generator go for memory based instructions or will necessarily have to go for a r egister based instruction only is to be considered.<\/p>\r\n \r\n\r\nWith these issues in consideration, the simple code generator algorithm uses two data structures to resolve, which is discussed in the next section.\r\n\r\n \r\n\r\n30.1.1 Data structures for the Simple code generator algorithm<\/strong>\r\n\r\n \r\n

This algorithm uses two data structures for generating code. The first one is the Register Descriptor which is used to keep track of which variable is currently stored in a register at\u00a0\u00a0particular<\/span> point in the code. The second data structure is referred to as address descriptor which is used to keep track of the location where the current value of the variable <\/span>ca n be found at <\/span>run time.<\/span><\/p>\r\n\r\n<\/div>\r\n

\r\n\r\n \r\n\r\nBoth these data structures are hash table and have the fields as given in Table 30.1\r\n\r\n \r\n\r\nTable 30.1 Register and Address Descriptor<\/strong>\r\n\r\n \r\n\r\n\r\n\r\n\r\n\r\n
Register Descriptor<\/strong><\/td>\r\nAddress Descriptor<\/strong><\/td>\r\n<\/tr>\r\n
Register Name<\/td>\r\nContents of the register<\/td>\r\nVariable Name<\/td>\r\nAvailable location<\/td>\r\n<\/tr>\r\n
<\/td>\r\n<\/td>\r\n<\/td>\r\n<\/td>\r\n<\/tr>\r\n<\/tbody>\r\n<\/table>\r\n \r\n\r\n \r\n\r\nFor example consider the following code:\r\n\r\n \r\n\r\nMOV a, R0 <\/strong>after this instruction is executed, the register descriptor of R0 will have its contents column updated as \u2018a\u2019.\r\n\r\nFor the following sequence of code, the contents of register descriptor of R0 and R1 will be \u2018a\u2019.\r\n\r\nThe contents of the address descriptor of the variable \u2018a\u2018will read R0<\/strong> and R1.<\/strong>\r\n\r\n \r\n\r\nMOV a, R0<\/strong>\r\n\r\nMOV R0, R1<\/strong>\r\n\r\n \r\n

A more simple description for register descriptor would be that, if we query \u201cregister name\u201d as input the output will be what variable it contains. On the other hand, if we query the \u201cvariable name\u201d to the address descriptor the output will be the location of the variable \u2018a\u2019, which could be address or register.<\/p>\r\n \r\n\r\n30.1.2 The Code Generation Algorithm<\/strong>\r\n\r\n \r\n\r\nAlgorithm 30.1 SimpleCodeGenerator( )\r\n\r\ninput : Sequence of 3-address statements from a basic block.\r\n\r\nOutput: Assembly language code\r\n\r\n \r\n\r\nFor each statement x<\/em> := y<\/em> op z<\/em>\r\n\r\n \r\n\r\n1.\u00a0\u00a0\u00a0\u00a0\u00a0 Set location L<\/em> = getreg<\/em>(y<\/em>, z<\/em>) to store the result of y op z\r\n\r\n2.\u00a0\u00a0\u00a0\u00a0\u00a0 If y<\/em> \u00cf L<\/em> then generate\r\n\r\n \r\n\r\nMOV <\/strong>y\u2019<\/em>,L<\/em>\r\n\r\n \r\n\r\nwhere y\u2019<\/em> denotes one of the locations where the value of y<\/em> is available - choose register if possible\r\n\r\n3.\u00a0\u00a0\u00a0 Generate\r\n\r\nOP <\/strong>z\u2019<\/em>,L<\/em>\r\n\r\n<\/div>\r\n

\r\n\r\nwhere z\u2019<\/em> is one of the locations of z<\/em>;\r\n\r\nUpdate register\/address descriptor of x<\/em> to include L<\/em>\r\n\r\n4.\u00a0\u00a0\u00a0\u00a0\u00a0 If y<\/em> and\/or z<\/em> has no next use and is stored in register, update register descriptors to remove y<\/em> and\/or z<\/em>\r\n\r\n \r\n

The first step in the algorithm is to invoke the getreg() function to get a register to store the result of the computation. The next step is to find the location of the first operand on the LHS. If it is in a register which is found by querying the address descriptor, then the same register is issued. The next step is issue a MOV command to transfer the variable\u2019s value into the register. If the variable is already in a register then this instruction could be eliminated. The next instruction is to operate on that register using the other operand and at this point the value of the LHS variable of the input instruction is in the register. So, the address descriptor and register descriptors are updated accordingly. The last step is to find out whether the current variable has a next-use immediately. Depending on the next-use the register content is copied to the variable and the descriptors are updated so that the register could be used for some other instructions.<\/p>\r\n \r\n\r\nAlgorithm 30.2 getreg ( )<\/strong>\r\n\r\n \r\n\r\nInput: Request for a register\r\n\r\n \r\n\r\nOutput: A register or the memory location\r\n

1.\u00a0\u00a0\u00a0\u00a0\u00a0 If y<\/em> is stored in a register R<\/em> and R<\/em> only holds the value y<\/em>, and y<\/em> has no next use, then return R<\/em>; Update address descriptor: value y<\/em> no longer in R<\/em><\/p>\r\n

2.\u00a0\u00a0\u00a0\u00a0\u00a0 Else, return a new empty register if available<\/p>\r\n

3.\u00a0\u00a0\u00a0\u00a0\u00a0 Else, find an occupied register R<\/em>;\u00a0 Store contents (register spill) by generating\u00a0 MOV R<\/em>,M\u00a0\u00a0<\/em>for every M<\/em> in address descriptor of y<\/em>; Return register R<\/em><\/p>\r\n

4.\u00a0\u00a0\u00a0\u00a0\u00a0 Else Return a memory location<\/p>\r\n \r\n

The getreg() function, returns a register if a free register is available. If the value of the variable for which we are trying to issue a MOV instruction is already in a register then the same register is used. If there are no free registers, then an occupied register is identified, it is freed by moving its contents to variable and then is issued. If no such free register could be identified, then the instruction operates on memory location.<\/p>\r\n \r\n\r\nConsider the following statement which is part of a high- level language:\r\n\r\n \r\n\r\nd := (a-b) + (a-c) + (a-c)\r\n\r\n<\/div>\r\nThe corresponding three- address code will be the following, where t, u, v, are temporary variables.\r\n

    \r\n \t
  • t: = a-b u := a-c v := t + u d := v +u<\/li>\r\n<\/ul>\r\nThe code generation sequence is given in Table 30.2.\r\n\r\n\"\"\r\n\r\n \r\n\r\n \r\n\r\nConsider the following example\r\n\r\n \r\n
      \r\n \t
    • x := y + z<\/li>\r\n \t
    • If x < 0 goto z<\/li>\r\n<\/ul>\r\nThe following would be the target code\r\n\r\n \r\n\r\nMOV y, R0\r\n\r\n \r\n\r\nADD z, R0\r\n\r\n \r\n\r\nMOV R0, x\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/\/ x is the condition code\r\n\r\n \r\n\r\nCJ < z\r\n\r\n \r\n\r\n30.2 Register Allocation<\/strong>\r\n\r\n \r\n

      A primary task of the compiler is register allocation for the variables. The number of registers available in any hardware architecture is very minimal compared to the number of variables that are defined in a particular piece of program. The getreg algorithm is simple but not optimal as the algorithm stores all live variables in registers till the end of a block. The register allocation problem is NP complete. Suppose, if we go in for Global register allocation which involves assigning variables to limited number of available registers and attempts to keep these registers consistent across basic block boundaries.<\/p>\r\n \r\n

      Keeping variables in registers in loops can be beneficial as it avoids register spilling. Suppose loading a variable x<\/em> has a cost of 2 and storing a variable x<\/em> has also a cost of 2, benefit of allocating a register to a variable x<\/em> within a loop L<\/em> is<\/p>\r\n\u00e5B<\/em>\u00ceL<\/em> ( use<\/em>(x<\/em>, B<\/em>) + 2 live<\/em>(x<\/em>, B<\/em>) )\r\n\r\n \r\n

      where use<\/em>(x<\/em>, B<\/em>) is the number of times x<\/em> is used in B<\/em> and live<\/em>(x<\/em>, B<\/em>) = true if x<\/em> is live on exit from\u00a0\u00a0B\u00a0\u00a0<\/em>Consider the example of basic block and control flow graph of figure 30.1:<\/p>\r\n \r\n\r\n\"\"\r\n\r\n\"\"\r\n

      From Table 30.4, we find the maximum cost associated with every variable. A dedicated register is given to the variable that has the maximum cost and is never disturbed during register spilling. A maximum cost indicates that variable is used and defined mo re.<\/p>\r\n \r\n

      Global Register Allocation can also be done using a graph coloring algorithm. When a register is needed and all available registers are in use, the content of one of the used registers must be stored to free a register and this is referred to as register spilling. Graph coloring allocates registers and attempts to minimize the cost of spills. An interference graph is built based on how variable interfere with each other. After constructing the graph, the graph coloring a lgorithm is applied to identify how many colors are at the least required to color this graph and this essentially translates to the number of registers required to compute the sequence of instructions.<\/p>\r\n \r\n

      Register interference graph is constructed with nodes indicating the variables which indirectly refer to the symbolic registers. An edge between nodes is established such that if one variable is live at a point where other is defined. For the first block B1 of the example in figure 30.1, the interference graph is shown in figure 30.2.<\/p>\r\n\"\"\r\n\r\nFor the graph of figure 30.2, two colors are required. Thus 2 registers are required to compute this basic block B1.\r\n\r\n \r\n\r\nSummary<\/strong>: To summarize, in this module we have discussed the simple code generator algorithm detailing on register descriptors and address descriptors. We also looked at the register allocation algorithm which is based on use and live statistics and also another methodology based on graph coloring.","rendered":"

      \n

      In this module we will try to learn the simple code generator algorithm. We shall also discuss the data structures involved in the simple code generator algorithm. We will conclude this module by understanding the algorithms for register allocation.<\/p>\n

       <\/p>\n

      30.1 Simple Code Generator<\/strong><\/p>\n

       <\/p>\n

      The simple code generator algorithm generates target code for a sequence of three-address statements. The code generator algorithm works by considering individually all the basic blocks. It uses the next-use information to decide on whether to keep the computation in the register or move it to a variable so that the register could be reused. The computation of next-use information is explained in the previous module. We assume that for each operator in the input statement there is a target- language operator. It uses new function getreg()<\/em> to assign registers to variables. The algorithm for code generation initially checks if operands to three-address code are available in registers. After computing the results of two operations, the results are kept in registers till the result is required by another computation or register is kept up to a procedure call or end of block to avoid errors.<\/p>\n

       <\/p>\n

      For example, consider the following instruction:<\/p>\n

       <\/p>\n

      \u2022\u00a0\u00a0\u00a0\u00a0\u00a0 a := b+c<\/p>\n

       <\/p>\n

      The following sequence would be followed by the code generator algorithm:<\/p>\n

      \u00b7\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 The algorithm initially checks if \u2018b\u2019 and \u2018c\u2019 are in registers Ri, Rj. If available then the instruction ADD Ri, Rj is generated and this costs 1 and the result is stored in Rj<\/p>\n

      \u2022\u00a0\u00a0\u00a0\u00a0\u00a0 If \u2018b\u2019 alone is in register and \u2018c\u2019 is not in the register, then the instruction ADD c, Ri is generated to a cost of 2<\/p>\n

      \u2022\u00a0\u00a0\u00a0\u00a0\u00a0 MOV a, Rj is issued to move the computation to \u2018a\u2019.<\/p>\n

       <\/p>\n

      The issues that need to be resolved are how to get the registers. If the registers are free then there is no issue. If the registers are all occupied, we must free an existing register. Will the instruction generator go for memory based instructions or will necessarily have to go for a r egister based instruction only is to be considered.<\/p>\n

       <\/p>\n

      With these issues in consideration, the simple code generator algorithm uses two data structures to resolve, which is discussed in the next section.<\/p>\n

       <\/p>\n

      30.1.1 Data structures for the Simple code generator algorithm<\/strong><\/p>\n

       <\/p>\n

      This algorithm uses two data structures for generating code. The first one is the Register Descriptor which is used to keep track of which variable is currently stored in a register at\u00a0\u00a0particular<\/span> point in the code. The second data structure is referred to as address descriptor which is used to keep track of the location where the current value of the variable <\/span>ca n be found at <\/span>run time.<\/span><\/p>\n<\/div>\n

      \n

       <\/p>\n

      Both these data structures are hash table and have the fields as given in Table 30.1<\/p>\n

       <\/p>\n

      Table 30.1 Register and Address Descriptor<\/strong><\/p>\n

       <\/p>\n\n\n\n\n\n
      Register Descriptor<\/strong><\/td>\nAddress Descriptor<\/strong><\/td>\n<\/tr>\n
      Register Name<\/td>\nContents of the register<\/td>\nVariable Name<\/td>\nAvailable location<\/td>\n<\/tr>\n
      <\/td>\n<\/td>\n<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

       <\/p>\n

       <\/p>\n

      For example consider the following code:<\/p>\n

       <\/p>\n

      MOV a, R0 <\/strong>after this instruction is executed, the register descriptor of R0 will have its contents column updated as \u2018a\u2019.<\/p>\n

      For the following sequence of code, the contents of register descriptor of R0 and R1 will be \u2018a\u2019.<\/p>\n

      The contents of the address descriptor of the variable \u2018a\u2018will read R0<\/strong> and R1.<\/strong><\/p>\n

       <\/p>\n

      MOV a, R0<\/strong><\/p>\n

      MOV R0, R1<\/strong><\/p>\n

       <\/p>\n

      A more simple description for register descriptor would be that, if we query \u201cregister name\u201d as input the output will be what variable it contains. On the other hand, if we query the \u201cvariable name\u201d to the address descriptor the output will be the location of the variable \u2018a\u2019, which could be address or register.<\/p>\n

       <\/p>\n

      30.1.2 The Code Generation Algorithm<\/strong><\/p>\n

       <\/p>\n

      Algorithm 30.1 SimpleCodeGenerator( )<\/p>\n

      input : Sequence of 3-address statements from a basic block.<\/p>\n

      Output: Assembly language code<\/p>\n

       <\/p>\n

      For each statement x<\/em> := y<\/em> op z<\/em><\/p>\n

       <\/p>\n

      1.\u00a0\u00a0\u00a0\u00a0\u00a0 Set location L<\/em> = getreg<\/em>(y<\/em>, z<\/em>) to store the result of y op z<\/p>\n

      2.\u00a0\u00a0\u00a0\u00a0\u00a0 If y<\/em> \u00cf L<\/em> then generate<\/p>\n

       <\/p>\n

      MOV <\/strong>y\u2019<\/em>,L<\/em><\/p>\n

       <\/p>\n

      where y\u2019<\/em> denotes one of the locations where the value of y<\/em> is available – choose register if possible<\/p>\n

      3.\u00a0\u00a0\u00a0 Generate<\/p>\n

      OP <\/strong>z\u2019<\/em>,L<\/em><\/p>\n<\/div>\n

      \n

      where z\u2019<\/em> is one of the locations of z<\/em>;<\/p>\n

      Update register\/address descriptor of x<\/em> to include L<\/em><\/p>\n

      4.\u00a0\u00a0\u00a0\u00a0\u00a0 If y<\/em> and\/or z<\/em> has no next use and is stored in register, update register descriptors to remove y<\/em> and\/or z<\/em><\/p>\n

       <\/p>\n

      The first step in the algorithm is to invoke the getreg() function to get a register to store the result of the computation. The next step is to find the location of the first operand on the LHS. If it is in a register which is found by querying the address descriptor, then the same register is issued. The next step is issue a MOV command to transfer the variable\u2019s value into the register. If the variable is already in a register then this instruction could be eliminated. The next instruction is to operate on that register using the other operand and at this point the value of the LHS variable of the input instruction is in the register. So, the address descriptor and register descriptors are updated accordingly. The last step is to find out whether the current variable has a next-use immediately. Depending on the next-use the register content is copied to the variable and the descriptors are updated so that the register could be used for some other instructions.<\/p>\n

       <\/p>\n

      Algorithm 30.2 getreg ( )<\/strong><\/p>\n

       <\/p>\n

      Input: Request for a register<\/p>\n

       <\/p>\n

      Output: A register or the memory location<\/p>\n

      1.\u00a0\u00a0\u00a0\u00a0\u00a0 If y<\/em> is stored in a register R<\/em> and R<\/em> only holds the value y<\/em>, and y<\/em> has no next use, then return R<\/em>; Update address descriptor: value y<\/em> no longer in R<\/em><\/p>\n

      2.\u00a0\u00a0\u00a0\u00a0\u00a0 Else, return a new empty register if available<\/p>\n

      3.\u00a0\u00a0\u00a0\u00a0\u00a0 Else, find an occupied register R<\/em>;\u00a0 Store contents (register spill) by generating\u00a0 MOV R<\/em>,M\u00a0\u00a0<\/em>for every M<\/em> in address descriptor of y<\/em>; Return register R<\/em><\/p>\n

      4.\u00a0\u00a0\u00a0\u00a0\u00a0 Else Return a memory location<\/p>\n

       <\/p>\n

      The getreg() function, returns a register if a free register is available. If the value of the variable for which we are trying to issue a MOV instruction is already in a register then the same register is used. If there are no free registers, then an occupied register is identified, it is freed by moving its contents to variable and then is issued. If no such free register could be identified, then the instruction operates on memory location.<\/p>\n

       <\/p>\n

      Consider the following statement which is part of a high- level language:<\/p>\n

       <\/p>\n

      d := (a-b) + (a-c) + (a-c)<\/p>\n<\/div>\n

      The corresponding three- address code will be the following, where t, u, v, are temporary variables.<\/p>\n

        \n
      • t: = a-b u := a-c v := t + u d := v +u<\/li>\n<\/ul>\n

        The code generation sequence is given in Table 30.2.<\/p>\n

        \"\"<\/p>\n

         <\/p>\n

         <\/p>\n

        Consider the following example<\/p>\n

         <\/p>\n

          \n
        • x := y + z<\/li>\n
        • If x < 0 goto z<\/li>\n<\/ul>\n

          The following would be the target code<\/p>\n

           <\/p>\n

          MOV y, R0<\/p>\n

           <\/p>\n

          ADD z, R0<\/p>\n

           <\/p>\n

          MOV R0, x\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 \/\/ x is the condition code<\/p>\n

           <\/p>\n

          CJ < z<\/p>\n

           <\/p>\n

          30.2 Register Allocation<\/strong><\/p>\n

           <\/p>\n

          A primary task of the compiler is register allocation for the variables. The number of registers available in any hardware architecture is very minimal compared to the number of variables that are defined in a particular piece of program. The getreg algorithm is simple but not optimal as the algorithm stores all live variables in registers till the end of a block. The register allocation problem is NP complete. Suppose, if we go in for Global register allocation which involves assigning variables to limited number of available registers and attempts to keep these registers consistent across basic block boundaries.<\/p>\n

           <\/p>\n

          Keeping variables in registers in loops can be beneficial as it avoids register spilling. Suppose loading a variable x<\/em> has a cost of 2 and storing a variable x<\/em> has also a cost of 2, benefit of allocating a register to a variable x<\/em> within a loop L<\/em> is<\/p>\n

          \u00e5B<\/em>\u00ceL<\/em> ( use<\/em>(x<\/em>, B<\/em>) + 2 live<\/em>(x<\/em>, B<\/em>) )<\/p>\n

           <\/p>\n

          where use<\/em>(x<\/em>, B<\/em>) is the number of times x<\/em> is used in B<\/em> and live<\/em>(x<\/em>, B<\/em>) = true if x<\/em> is live on exit from\u00a0\u00a0B\u00a0\u00a0<\/em>Consider the example of basic block and control flow graph of figure 30.1:<\/p>\n

           <\/p>\n

          \"\"<\/p>\n

          \"\"<\/p>\n

          From Table 30.4, we find the maximum cost associated with every variable. A dedicated register is given to the variable that has the maximum cost and is never disturbed during register spilling. A maximum cost indicates that variable is used and defined mo re.<\/p>\n

           <\/p>\n

          Global Register Allocation can also be done using a graph coloring algorithm. When a register is needed and all available registers are in use, the content of one of the used registers must be stored to free a register and this is referred to as register spilling. Graph coloring allocates registers and attempts to minimize the cost of spills. An interference graph is built based on how variable interfere with each other. After constructing the graph, the graph coloring a lgorithm is applied to identify how many colors are at the least required to color this graph and this essentially translates to the number of registers required to compute the sequence of instructions.<\/p>\n

           <\/p>\n

          Register interference graph is constructed with nodes indicating the variables which indirectly refer to the symbolic registers. An edge between nodes is established such that if one variable is live at a point where other is defined. For the first block B1 of the example in figure 30.1, the interference graph is shown in figure 30.2.<\/p>\n

          \"\"<\/p>\n

          For the graph of figure 30.2, two colors are required. Thus 2 registers are required to compute this basic block B1.<\/p>\n

           <\/p>\n

          Summary<\/strong>: To summarize, in this module we have discussed the simple code generator algorithm detailing on register descriptors and address descriptors. We also looked at the register allocation algorithm which is based on use and live statistics and also another methodology based on graph coloring.<\/p>\n","protected":false},"author":4,"menu_order":30,"template":"","meta":{"pb_show_title":"on","pb_short_title":"","pb_subtitle":"","pb_authors":["dr-rajeswari-sridhar"],"pb_section_license":""},"chapter-type":[],"contributor":[59],"license":[],"class_list":["post-258","chapter","type-chapter","status-publish","hentry","contributor-dr-rajeswari-sridhar"],"part":3,"_links":{"self":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/chapters\/258","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/chapters"}],"about":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/wp\/v2\/types\/chapter"}],"author":[{"embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/wp\/v2\/users\/4"}],"version-history":[{"count":2,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/chapters\/258\/revisions"}],"predecessor-version":[{"id":265,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/chapters\/258\/revisions\/265"}],"part":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/parts\/3"}],"metadata":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/chapters\/258\/metadata\/"}],"wp:attachment":[{"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/wp\/v2\/media?parent=258"}],"wp:term":[{"taxonomy":"chapter-type","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/pressbooks\/v2\/chapter-type?post=258"},{"taxonomy":"contributor","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/wp\/v2\/contributor?post=258"},{"taxonomy":"license","embeddable":true,"href":"https:\/\/ebooks.inflibnet.ac.in\/csp10\/wp-json\/wp\/v2\/license?post=258"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}